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11. 发明申请

US20100102290A1 SILICON BASED NANOSCALE CROSSBAR MEMORY 有权
标题翻译：基于硅的NANOSCALE十字路口存储器
公开(公告)号：US20100102290A1
公开(公告)日：2010-04-29
申请号：US12582086
申请日：2009-10-20
申请人： Wei Lu , Sung Hyun Jo , Kuk-Hwan Kim
发明人： Wei Lu , Sung Hyun Jo , Kuk-Hwan Kim
IPC分类号： H01L47/00
CPC分类号： H01L45/1253 , B82Y10/00 , B82Y30/00 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/005 , G11C2013/0071 , G11C2213/11 , G11C2213/33 , G11C2213/77 , G11C2213/81 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1266 , H01L45/148 , H01L45/1608 , H01L45/1675
摘要： The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.
摘要翻译：本申请描述了一种交叉开关存储器阵列。存储器阵列包括第一材料的平行纳米线的第一阵列和第二材料的平行纳米线的第二阵列。第一和第二阵列彼此成一角度定向。阵列还包括布置在第一材料的纳米线和第二材料的纳米线之间的两个阵列的每个交叉处的非晶硅的多个纳米结构。纳米结构与第一和第二材料的纳米线一起形成电阻记忆单元。

12. 发明申请

US20090014707A1 NON-VOLATILE SOLID STATE RESISTIVE SWITCHING DEVICES 审中-公开
标题翻译：非挥发性固态电阻开关器件
公开(公告)号：US20090014707A1
公开(公告)日：2009-01-15
申请号：US11875541
申请日：2007-10-19
申请人： Wei Lu , Sung Hyun Jo
发明人： Wei Lu , Sung Hyun Jo
IPC分类号： H01L45/00
CPC分类号： H01L45/14 , H01L27/2472 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/148 , H01L45/1616 , H01L45/1675
摘要： Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer.
摘要翻译：非晶硅非易失性电阻开关器件包括金属电极，非晶硅层和平面掺杂硅电极。施加到金属电极的电信号将金属离子从金属电极驱动到非晶硅层，以形成从金属电极到平面掺杂硅电极的导电丝，以改变非晶硅层的电阻。施加到金属电极的另一电信号从非晶硅层去除形成导电丝的至少一些金属离子，以进一步改变非晶硅层的电阻。

13. 发明授权

US09012307B2 Two terminal resistive switching device structure and method of fabricating 有权
标题翻译：两端电阻开关器件结构及其制造方法
公开(公告)号：US09012307B2
公开(公告)日：2015-04-21
申请号：US12835704
申请日：2010-07-13
申请人： Sung Hyun Jo , Scott Brad Herner
发明人： Sung Hyun Jo , Scott Brad Herner
IPC分类号： H01L21/82 , H01L21/20 , H01L45/00
CPC分类号： H01L45/085 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/14 , H01L45/143 , H01L45/148 , H01L45/16 , H01L45/1675
摘要： A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A top wiring material including a conductive material is formed overlying at lease the opening region such that the conductive material is in direct contact with the switching element. A second etching process is performed to form at least a top wiring structure. In a specific embodiment, the side region of the first structure including a first side region of the switching element is free from a contaminant conductive material from the second etching process.
摘要翻译：一种形成两个终端设备的方法。该方法包括形成覆盖在衬底的表面区域上的第一电介质材料。底部布线材料形成在第一介电材料上方，并且覆盖在底部布线材料上的开关材料沉积。对底部布线材料和开关材料进行第一图案化和蚀刻工艺以形成具有顶表面区域和侧面区域的第一结构。第一结构至少包括底部布线结构和具有第一侧面区域的开关元件和包括开关元件的暴露区域的顶表面区域。至少形成包括开关元件的暴露区域的第一结构的第二电介质材料。该方法在第二电介质层的一部分中形成开口区域，以露出开关元件的顶表面区域的一部分。包括导电材料的顶部布线材料形成为覆盖开口区域，使得导电材料与开关元件直接接触。执行第二蚀刻工艺以形成至少顶部布线结构。在具体实施例中，包括开关元件的第一侧区域的第一结构的侧面区域没有来自第二蚀刻工艺的污染物导电材料。

14. 发明授权

US08946046B1 Guided path for forming a conductive filament in RRAM 有权
标题翻译：在RRAM中形成导电细丝的引导路径
公开(公告)号：US08946046B1
公开(公告)日：2015-02-03
申请号：US13462653
申请日：2012-05-02
申请人： Sung Hyun Jo
发明人： Sung Hyun Jo
IPC分类号： H01L21/20 , H01L21/4763 , H01L45/00
CPC分类号： H01L45/06 , H01L21/4763 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/148 , H01L45/1675 , H01L45/1683
摘要： A method of forming a non-volatile memory device, includes forming a first electrode above a substrate, forming a dielectric layer overlying the first electrode, forming an opening structure in a portion of the dielectric layer to expose a surface of the first electrode having an aspect ratio, forming a resistive switching material overlying the dielectric layer and filling at least a portion of the opening structure using a deposition process, the resistive switching material having a surface region characterized by a planar region and an indent structure, the indent structure overlying the first electrode, maintaining a first thickness of resistive switching material between the planar region and the first electrode, maintaining a second thickness of resistive switching material between the indent structure and the first electrode, wherein the first thickness is larger than the second thickness, and forming a second electrode overlying the resistive switching material including the indent structure.
摘要翻译：一种形成非易失性存储器件的方法，包括在衬底上形成第一电极，形成覆盖在第一电极上的电介质层，在电介质层的一部分中形成开口结构，以暴露第一电极的表面，形成覆盖在电介质层上的电阻性开关材料，并且使用沉积工艺填充至少一部分开口结构，所述电阻开关材料具有由平面区域和缩进结构表征的表面区域，所述凹陷结构覆盖第一电极，在所述平面区域和所述第一电极之间保持第一厚度的电阻性切换材料，在所述凹陷结构和所述第一电极之间保持电阻性切换材料的第二厚度，其中所述第一厚度大于所述第二厚度，覆盖电阻式开关材料的第二电极，包括i 结构。

15. 发明授权

US08558212B2 Conductive path in switching material in a resistive random access memory device and control 有权
标题翻译：电阻随机存取存储器件中的开关材料中的导电路径和控制
公开(公告)号：US08558212B2
公开(公告)日：2013-10-15
申请号：US12894098
申请日：2010-09-29
申请人： Sung Hyun Jo
发明人： Sung Hyun Jo
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/12 , H01L45/085 , H01L45/1233 , H01L45/148
摘要： A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material.
摘要翻译：非易失性存储器件结构。器件结构包括第一电极，第二电极，包括覆盖在第一电极上的非晶硅材料的电阻开关材料，以及设置在第二电极和电阻器之间的厚度范围为5nm至10nm的介电材料的厚度开关层。介电材料的厚度被配置为在向第二电极施加电铸电压时在区域中电击穿。电击穿允许在电阻开关材料的一部分中形成尺寸小于约10nm×10nm的金属区域。

16. 发明授权

US08441835B2 Interface control for improved switching in RRAM 有权
公开(公告)号：US08441835B2
公开(公告)日：2013-05-14
申请号：US12814410
申请日：2010-06-11
申请人： Sung Hyun Jo , Hagop Nazarian , Wei Lu
发明人： Sung Hyun Jo , Hagop Nazarian , Wei Lu
IPC分类号： G11C11/00
CPC分类号： H01L45/1608 , G11C13/0002 , G11C2213/33 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/148
摘要： A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell.

17. 发明授权

US08411485B2 Non-volatile variable capacitive device including resistive memory cell 有权
公开(公告)号：US08411485B2
公开(公告)日：2013-04-02
申请号：US12815318
申请日：2010-06-14
申请人： Hagop Nazarian , Sung Hyun Jo
发明人： Hagop Nazarian , Sung Hyun Jo
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C14/0045 , G11C2213/33 , G11C2213/53 , H01L29/7881 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/148
摘要： A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed in a plurality of resistive states according to an electrical signal received. The upper electrode of the capacitive device is coupled to the second electrode of the resistive memory cell. The resistive memory cell is a two-terminal device.

18. 发明申请

US20120320660A1 WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE 有权
标题翻译：电阻式存储器件的写入和擦除方案
公开(公告)号：US20120320660A1
公开(公告)日：2012-12-20
申请号：US13592224
申请日：2012-08-22
申请人： Hagop NAZARIAN , Sung Hyun Jo
发明人： Hagop NAZARIAN , Sung Hyun Jo
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0064 , G11C2013/0066 , G11C2213/15 , G11C2213/33
摘要： A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value.
摘要翻译：一种用于编程两端电阻式存储器件的方法，所述方法包括：将偏置电压施加到所述器件的电阻存储器单元的第一电极; 测量流过电池的电流; 如果测量的电流等于或大于预定值，则停止施加偏置电压。

19. 发明申请

US20120049149A1 SILICON BASED NANOSTRUCTURE CROSSBAR MEMORY 有权
标题翻译：基于硅的纳米结构记录
公开(公告)号：US20120049149A1
公开(公告)日：2012-03-01
申请号：US13291094
申请日：2011-11-07
申请人： Wei Lu , Sung Hyun Jo , Kuk-Hwan Kim
发明人： Wei Lu , Sung Hyun Jo , Kuk-Hwan Kim
IPC分类号： H01L47/00 , B82Y10/00
CPC分类号： H01L45/1253 , B82Y10/00 , B82Y30/00 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/005 , G11C2013/0071 , G11C2213/11 , G11C2213/33 , G11C2213/77 , G11C2213/81 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1266 , H01L45/148 , H01L45/1608 , H01L45/1675
摘要： The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.
摘要翻译：本申请描述了一种交叉开关存储器阵列。存储器阵列包括第一材料的平行纳米线的第一阵列和第二材料的平行纳米线的第二阵列。第一和第二阵列彼此成一角度定向。阵列还包括布置在第一材料的纳米线和第二材料的纳米线之间的两个阵列的每个交叉处的非晶硅的多个纳米结构。纳米结构与第一和第二材料的纳米线一起形成电阻记忆单元。

20. 发明申请

US20100085798A1 SILICON-BASED NANOSCALE RESISTIVE DEVICE WITH ADJUSTABLE RESISTANCE 有权
标题翻译：基于硅的纳米电阻器件具有可调电阻
公开(公告)号：US20100085798A1
公开(公告)日：2010-04-08
申请号：US12575921
申请日：2009-10-08
申请人： Wei Lu , Sung Hyun Jo , Kuk-Hwan Kim
发明人： Wei Lu , Sung Hyun Jo , Kuk-Hwan Kim
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C13/0002 , G11C13/003 , G11C2213/11 , G11C2213/15 , G11C2213/33 , G11C2213/72 , G11C2213/76 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/148
摘要： A non-volatile solid state resistive device that includes a first electrode, a p-type poly-silicon second electrode, and a non-crystalline silicon nanostructure electrically connected between the electrodes. The nanostructure has a resistance that is adjustable in response to a voltage being applied to the nanostructure via the electrodes. The nanostructure can be formed as a nanopillar embedded in an insulating layer located between the electrodes. The first electrode can be a silver or other electrically conductive metal electrode. A third (metal) electrode can be connected to the p-type poly-silicon second electrode at a location adjacent the nanostructure to permit connection of the two metal electrodes to other circuitry. The resistive device can be used as a unit memory cell of a digital non-volatile memory device to store one or more bits of digital data by varying its resistance between two or more values.
摘要翻译：一种非挥发性固态电阻器件，其包括电连接在电极之间的第一电极，p型多晶硅第二电极和非晶硅纳米结构。纳米结构具有响应于通过电极施加到纳米结构的电压而可调节的电阻。纳米结构可以形成为嵌入位于电极之间的绝缘层中的纳米柱。第一电极可以是银或其它导电金属电极。第三（金属）电极可以在邻近纳米结构的位置处连接到p型多晶硅第二电极，以允许两个金属电极连接到其它电路。电阻器件可以用作数字非易失性存储器件的单元存储单元，以通过改变其两个或多个值之间的电阻来存储一位或多位数字数据。

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