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11. 发明授权

US06828240B2 Method of manufacturing multi-level contacts by sizing of contact sizes in integrated circuits 有权
标题翻译：通过集成电路中接触尺寸的尺寸来制造多电平触点的方法
公开(公告)号：US06828240B2
公开(公告)日：2004-12-07
申请号：US10210995
申请日：2002-08-02
申请人： Kay Hellig , Massud Aminpur
发明人： Kay Hellig , Massud Aminpur
IPC分类号： H01L21311
CPC分类号： H01L21/76816
摘要： A method for forming an integrated circuit includes etching a first opening to a first depth in a dielectric material over a semiconductor device on a first semiconductor substrate and etching a second opening to a second depth in the dielectric material over the first semiconductor substrate. The first and second openings are differently sized to respectively etch to the first and second depths in about the same time due to etch lag. The first and second openings are filled with conductive material.
摘要翻译：一种用于形成集成电路的方法包括：在第一半导体衬底上的半导体器件上蚀刻电介质材料中的第一深度的第一开口，并在第一半导体衬底上蚀刻电介质材料中的第二深度。第一和第二开口具有不同的尺寸以分别由于蚀刻滞后在大约相同的时间内蚀刻到第一和第二深度。第一和第二开口用导电材料填充。

12. 发明授权

US07309654B2 Technique for reducing etch damage during the formation of vias and trenches in interlayer dielectrics 失效
标题翻译：用于在层间电介质形成通孔和沟槽期间减少蚀刻损伤的技术
公开(公告)号：US07309654B2
公开(公告)日：2007-12-18
申请号：US11380094
申请日：2006-04-25
申请人： Matthias Schaller , Massud Aminpur , James Werking
发明人： Matthias Schaller , Massud Aminpur , James Werking
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31144 , H01L21/76801 , H01L21/76802 , H01L21/76808
摘要： By performing a first common etch process for forming a via opening and a delineation trench or open area in a metallization layer with different removal rates, the etch front in the delineation trench or open area may be delayed, thereby significantly reducing the probability of wafer arcing. Subsequently, the delineation trench or open area may be etched down to the respective etch stop layer in a further common etch process, during which a trench is formed above the via opening.
摘要翻译：通过执行用于在具有不同去除速率的金属化层中形成通孔开口和描绘沟槽或开口区域的第一常用蚀刻工艺，可以延迟描绘沟槽或开放区域中的蚀刻前沿，从而显着降低晶片电弧的可能性。随后，在另一常见的蚀刻工艺中，描绘沟槽或开放区域可以被蚀刻到相应的蚀刻停止层，在此期间在通孔开口上方形成沟槽。

13. 发明申请

US20060046495A1 Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches 有权
标题翻译：用于通过沟槽边缘四舍五入来增强电化学沉积过程中的填充能力的技术
公开(公告)号：US20060046495A1
公开(公告)日：2006-03-02
申请号：US11122591
申请日：2005-05-05
申请人： Kai Frohberg , Matthias Schaller , Massud Aminpur
发明人： Kai Frohberg , Matthias Schaller , Massud Aminpur
IPC分类号： H01L21/461
CPC分类号： H01L21/76804 , H01L21/7688
摘要： During the formation of a metal line in a low-k dielectric material, an upper portion of a trench formed in a capping layer and the low-k dielectric material is treated to provide enlarged tapering or corner rounding, thereby significantly improving the fill capabilities of subsequent metal deposition processes. In one particular embodiment, an additional etch process is performed after etching through the capping layer and the low-k dielectric layer and after resist removal.
摘要翻译：在低k电介质材料中形成金属线时，形成在封盖层中的沟槽的上部和低k电介质材料被处理以提供扩大的锥形或圆角圆化，从而显着提高填充能力随后的金属沉积工艺。在一个特定实施例中，在蚀刻通过覆盖层和低k电介质层之后并且在抗蚀剂移除之后执行附加蚀刻工艺。

14. 发明授权

US07005380B2 Simultaneous formation of device and backside contacts on wafers having a buried insulator layer 有权
标题翻译：在具有掩埋绝缘体层的晶片上同时形成器件和背面触点
公开(公告)号：US07005380B2
公开(公告)日：2006-02-28
申请号：US10446974
申请日：2003-05-28
申请人： Massud Aminpur , Gert Burbach , Christian Zistl
发明人： Massud Aminpur , Gert Burbach , Christian Zistl
IPC分类号： H01L21/302
CPC分类号： H01L21/743 , H01L21/76802 , H01L21/76838 , H01L21/84 , H01L27/1203 , Y10S438/96
摘要： A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.
摘要翻译：提供一种半导体器件制造方法，其中在包括背面半导体衬底，埋入绝缘体层和顶部半导体层的晶片的顶部上形成器件结构。然后，在承载器件结构的晶片上形成蚀刻停止层，并且在蚀刻停止层中形成窗口。此外，在具有窗口的蚀刻停止层上形成介电层。然后，通过电介质层和向下到半导体衬底的窗口的第一接触孔同时被至少一个通过介电层的第二接触孔蚀刻到器件结构。晶片可以是绝缘体上硅（SOI）晶片，并且蚀刻停止层和电介质层可以分别通过沉积氮氧化硅和原硅酸四乙酯（TEOS）来形成。器件结构可以是CMOS晶体管结构。

15. 发明授权

US07517816B2 Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress 有权
标题翻译：通过形成具有不同修正的固有应力的蚀刻停止层，在不同通道区域中产生不同的机械应力的技术
公开(公告)号：US07517816B2
公开(公告)日：2009-04-14
申请号：US11058035
申请日：2005-02-15
申请人： Kai Frohberg , Matthias Schaller , Massud Aminpur
发明人： Kai Frohberg , Matthias Schaller , Massud Aminpur
IPC分类号： H01L21/31 , H01L21/469 , H01L21/8238
CPC分类号： H01L21/76829 , H01L21/76832 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L29/7842 , H01L29/7843
摘要： By providing a contact etch stop layer, the stress in channel regions of different transistor types may be effectively controlled, wherein tensile and compressive stress portions of the contact etch stop layer may be obtained by well-established processes, such as wet chemical etch, plasma etch, ion implantation, plasma treatment and the like. Hence, a significant improvement in transistor performance may be obtained while not significantly contributing to process complexity.
摘要翻译：通过提供接触蚀刻停止层，可以有效地控制不同晶体管类型的沟道区域中的应力，其中接触蚀刻停止层的拉伸和压缩应力部分可以通过公认的工艺获得，例如湿化学蚀刻，等离子体蚀刻，离子注入，等离子体处理等。因此，可以获得晶体管性能的显着改善，而不会对工艺复杂性造成重大影响。

16. 发明授权

US07256113B1 System for forming a semiconductor device and method thereof 有权
标题翻译：用于形成半导体器件的系统及其方法
公开(公告)号：US07256113B1
公开(公告)日：2007-08-14
申请号：US10058708
申请日：2002-01-28
申请人： Kay Hellig , Phillip E. Crabtree , Massud Aminpur
发明人： Kay Hellig , Phillip E. Crabtree , Massud Aminpur
IPC分类号： H01L21/28
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66598 , H01L29/7833
摘要： A method for fabricating sidewall spacers in the manufacture of an integrated circuit device is disclosed. A dielectric spacer layer is formed over the semiconductor substrate. The dielectric spacer layer is etched prior to forming a layer subsequent to the dielectric layer, to form an L-shaped spacer. In another embodiment, a structure is formed on a substrate, the structure having a sidewall portion that is substantially orthogonal to a surface of the substrate. A dielectric layer is formed over the substrate. A spacer is formed over a portion of the dielectric layer and adjacent to the sidewall portion of the structure, wherein at least a portion of the dielectric layer over the substrate without an overlying oxide spacer is an unprotected portion of the dielectric. At least a part of the unprotected portion of the dielectric layer is removed. An intermediate source-drain region can be formed beneath a portion of the L-shaped spacer by controlling the thickness and/or the source drain doping levels.
摘要翻译：公开了一种在制造集成电路器件中制造侧壁间隔物的方法。在半导体衬底上形成电介质间隔层。在形成电介质层之后的层之前蚀刻电介质间隔层，以形成L形间隔物。在另一个实施例中，在衬底上形成结构，该结构具有基本上垂直于衬底表面的侧壁部分。介电层形成在衬底上。间隔物形成在电介质层的一部分上并与结构的侧壁部分相邻，其中绝缘层上的至少一部分电介质层没有上覆的氧化物间隔物是电介质的未被保护的部分。去除介电层的未保护部分的至少一部分。通过控制厚度和/或源极漏极掺杂水平，可以在L形间隔物的一部分之下形成中间源极 - 漏极区。

17. 发明授权

US08101524B2 Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches 有权
标题翻译：用于通过沟槽边缘四舍五入来增强电化学沉积过程中的填充能力的技术
公开(公告)号：US08101524B2
公开(公告)日：2012-01-24
申请号：US11122591
申请日：2005-05-05
申请人： Kai Frohberg , Matthias Schaller , Massud Aminpur
发明人： Kai Frohberg , Matthias Schaller , Massud Aminpur
IPC分类号： H01L21/462
CPC分类号： H01L21/76804 , H01L21/7688
摘要： During the formation of a metal line in a low-k dielectric material, an upper portion of a trench formed in a capping layer and the low-k dielectric material is treated to provide enlarged tapering or corner rounding, thereby significantly improving the fill capabilities of subsequent metal deposition processes. In one particular embodiment, an additional etch process is performed after etching through the capping layer and the low-k dielectric layer and after resist removal.
摘要翻译：在低k电介质材料中形成金属线时，形成在封盖层中的沟槽的上部和低k电介质材料被处理以提供扩大的锥形或拐角四舍五入，从而显着提高填充能力随后的金属沉积工艺。在一个特定实施例中，在蚀刻通过覆盖层和低k电介质层之后并且在抗蚀剂移除之后执行附加蚀刻工艺。

18. 发明申请

US20070004214A1 TECHNIQUE FOR REDUCING ETCH DAMAGE DURING THE FORMATION OF VIAS AND TRENCHES IN INTERLAYER DIELECTRICS 失效
标题翻译：在中间层电介质中形成VIAS和TRENCHES时减少蚀刻损伤的技术
公开(公告)号：US20070004214A1
公开(公告)日：2007-01-04
申请号：US11380094
申请日：2006-04-25
申请人： Matthias Schaller , Massud Aminpur , James Werking
发明人： Matthias Schaller , Massud Aminpur , James Werking
IPC分类号： H01L21/311 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , H01L21/31144 , H01L21/76801 , H01L21/76802 , H01L21/76808
摘要： By performing a first common etch process for forming a via opening and a delineation trench or open area in a metallization layer with different removal rates, the etch front in the delineation trench or open area may be delayed, thereby significantly reducing the probability of wafer arcing. Subsequently, the delineation trench or open area may be etched down to the respective etch stop layer in a further common etch process, during which a trench is formed above the via opening.
摘要翻译：通过执行用于在具有不同去除速率的金属化层中形成通孔开口和描绘沟槽或开口区域的第一常用蚀刻工艺，可以延迟描绘沟槽或开放区域中的蚀刻前沿，从而显着降低晶片电弧的可能性。随后，在另一常见的蚀刻工艺中，描绘沟槽或开放区域可以被蚀刻到相应的蚀刻停止层，在此期间在通孔开口上方形成沟槽。

19. 发明申请

US20050266639A1 Techique for controlling mechanical stress in a channel region by spacer removal 有权
标题翻译：用于通过间隔物去除来控制通道区域中的机械应力的技术
公开(公告)号：US20050266639A1
公开(公告)日：2005-12-01
申请号：US11047129
申请日：2005-01-31
申请人： Kai Frohberg , Matthias Schaller , Massud Aminpur , Martin Mazur , Roberto Klingler
发明人： Kai Frohberg , Matthias Schaller , Massud Aminpur , Martin Mazur , Roberto Klingler
IPC分类号： H01L21/3215 , H01L21/336 , H01L21/8238 , H01L29/49
CPC分类号： H01L29/6653 , H01L21/3215 , H01L21/32155 , H01L21/823807 , H01L21/823864 , H01L29/4966 , H01L29/665 , H01L29/7843 , Y10S438/938
摘要： During the formation of a transistor element, sidewalls spacers are removed or at least partially etched back after ion implantation and silicidation, thereby rendering the mechanical coupling of a contact etch stop layer to the underlying drain and source regions more effective. Hence, the mechanical stress may be substantially induced by the contact etch step layer rather than by a combination of the spacer elements and the etch stop layer, thereby significantly facilitating the stress engineering in the channel region. By additionally performing a plasma treatment, different amounts of stress may be created in different transistor devices without unduly contributing to process complexity.
摘要翻译：在形成晶体管元件期间，在离子注入和硅化之后去除侧壁间隔物或至少部分地回蚀，从而使接触蚀刻停止层与潜在的漏极和源极区域的机械耦合更有效。因此，机械应力可以基本上由接触蚀刻步骤层引起，而不是间隔元件和蚀刻停止层的组合，从而显着地促进了沟道区域中的应力工程。通过额外进行等离子体处理，可以在不同的晶体管器件中产生不同量的应力，而不会不利地导致工艺复杂性。

20. 发明申请

US20050263825A1 Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress 有权
标题翻译：通过形成具有不同修正的固有应力的蚀刻停止层，在不同通道区域中产生不同的机械应力的技术
公开(公告)号：US20050263825A1
公开(公告)日：2005-12-01
申请号：US11058035
申请日：2005-02-15
申请人： Kai Frohberg , Matthias Schaller , Massud Aminpur
发明人： Kai Frohberg , Matthias Schaller , Massud Aminpur
IPC分类号： H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L29/772
CPC分类号： H01L21/76829 , H01L21/76832 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L29/7842 , H01L29/7843
摘要： By providing a contact etch stop layer, the stress in channel regions of different transistor types may be effectively controlled, wherein tensile and compressive stress portions of the contact etch stop layer may be obtained by well-established processes, such as wet chemical etch, plasma etch, ion implantation, plasma treatment and the like. Hence, a significant improvement in transistor performance may be obtained while not significantly contributing to process complexity.
摘要翻译：通过提供接触蚀刻停止层，可以有效地控制不同晶体管类型的沟道区域中的应力，其中接触蚀刻停止层的拉伸和压缩应力部分可以通过公认的工艺获得，例如湿化学蚀刻，等离子体蚀刻，离子注入，等离子体处理等。因此，可以获得晶体管性能的显着改善，而不会对工艺复杂性造成重大影响。

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