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    • 11. 发明授权
    • Processor with multiple-thread, vertically-threaded pipeline
    • 处理器采用多线程,垂直螺纹管线
    • US06938147B1
    • 2005-08-30
    • US09309732
    • 1999-05-11
    • William N. JoyMarc TremblayGary LauterbachJoseph I. Chamdani
    • William N. JoyMarc TremblayGary LauterbachJoseph I. Chamdani
    • G06F9/38G06F9/48G06F9/00
    • G06F9/4843G06F9/3851
    • A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.
    • 处理器通过支持和实现垂直多线程和水平多线程来减少由于停滞和空闲而导致的浪费周期时间,并增加执行时间的比例。 垂直多线程允许重叠或“隐藏”高速缓存未命中等待时间。 在垂直多线程中,多个硬件线程共享相同的处理器管道。 在支持多线程的操作系统中,硬件线程通常是进程,轻量级进程,本机线程等。 水平多线程增加了处理器电路结构内的并行性,例如在构成单片处理器的单个集成电路管芯内。 为了在一些处理器实施例中进一步增加系统并行性,在单个管芯中形成多个处理器核。 通过技术进步降低了处理器核心尺寸,从而获得片上多处理器水平线程的进步。
    • 12. 发明授权
    • Combining results of selectively executed remaining sub-instructions with that of emulated sub-instruction causing exception in VLIW processor
    • 将选择执行的剩余子指令的结果与在VLIW处理器中引起异常的仿真子指令的结果相结合
    • US06405300B1
    • 2002-06-11
    • US09273602
    • 1999-03-22
    • Marc TremblayWilliam N. Joy
    • Marc TremblayWilliam N. Joy
    • G06F944
    • G06F9/3017G06F9/30101G06F9/3853G06F9/3861G06F9/3885
    • One embodiment of the present invention provides a system that efficiently emulates sub-instructions in a very long instruction word (VLIW) processor. The system operates by receiving an exception condition during execution of a VLIW instruction within a VLIW program. This exception condition indicates that at least one sub-instruction within the VLIW instruction requires emulation in software or software assistance. In processing this exception condition, the system emulates the sub-instructions that require emulation in software and stores the results. The system also selectively executes in hardware any remaining sub-instructions in the VLIW instruction that do not require emulation in software. The system finally combines the results from the sub-instructions emulated in software with the results from the remaining sub-instructions executed in hardware, and resumes execution of the VLIW program.
    • 本发明的一个实施例提供了一种在非常长的指令字(VLIW)处理器中有效地模拟子指令的系统。 该系统通过在VLIW程序中执行VLIW指令期间接收到异常情况来进行操作。 该异常条件表示VLIW指令中的至少一个子指令需要软件或软件协助进行仿真。 在处理此异常情况时,系统会模拟需要软件仿真并存储结果的子指令。 该系统还在硬件中选择性地执行VLIW指令中的任何剩余子指令,这些指令不需要软件仿真。 系统最终将从软件中仿真的子指令的结果与硬件中执行的剩余子指令的结果相结合,并恢复VLIW程序的执行。
    • 14. 发明授权
    • Computer system and method for executing threads of execution with
reduced run-time memory space requirements
    • 用于执行执行线程的计算机系统和方法,减少运行时存储空间要求
    • US5765157A
    • 1998-06-09
    • US658501
    • 1996-06-05
    • Timothy G. LindholmWilliam N. Joy
    • Timothy G. LindholmWilliam N. Joy
    • G06F12/02G06F9/44G06F9/46G06F9/48G06F12/06G06F13/00
    • G06F9/4843Y10S707/99942Y10S707/99953
    • A computer system and associated method for executing a plurality of threads of execution with reduced memory space requirements. The computer system comprises a memory, an execution controller, and a data compressor. The execution controller controls execution of the threads such that the threads are executable and unexecutable at different times. The execution controller also stores uncompressed into available space in the run-time memory execution data of the threads when the execution data is generated. The data compressor compresses the uncompressed execution data of compressible ones of the threads that are unexecutable. As a result, space is made available in the run-time memory. The data compressor also decompresses in available space in the run-time memory the compressed execution data of decompressible ones of the threads so that the decompressible ones of the threads may be executed after becoming executable.
    • 一种用于以减少的存储器空间要求执行多个执行线程的计算机系统和相关联的方法。 计算机系统包括存储器,执行控制器和数据压缩器。 执行控制器控制线程的执行,使得线程在不同时间是可执行的和不可执行的。 当生成执行数据时,执行控制器还将未压缩的存储空间存储在线程的运行时存储器执行数据中。 数据压缩器压缩不可执行的可压缩线程的未压缩执行数据。 因此,运行时存储器中提供了空间。 数据压缩器还在运行时存储器中的可用空间中解压缩可解压缩线程的压缩执行数据,使得可解压缩的线程可以在变为可执行之后被执行。
    • 19. 发明授权
    • Thread switch logic in a multiple-thread processor
    • 线程切换逻辑在多线程处理器中
    • US06341347B1
    • 2002-01-22
    • US09309733
    • 1999-05-11
    • William N. JoyMarc TremblayGary LauterbachJoseph I. Chamdani
    • William N. JoyMarc TremblayGary LauterbachJoseph I. Chamdani
    • G06F930
    • G06F9/4843G06F9/3851G06F12/0897
    • A processor includes a thread switching control logic that performs a fast thread-switching operation in response to an L1 cache miss stall. The fast thread-switching operation implements one or more of several thread-switching methods. A first thread-switching operation is “oblivious” thread-switching for every N cycle in which the individual flip-flops locally determine a thread-switch without notification of stalling. The oblivious technique avoids usage of an extra global interconnection between threads for thread selection. A second thread-switching operation is “semi-oblivious” thread-switching for use with an existing “pipeline stall” signal (if any). The pipeline stall signal operates in two capacities, first as a notification of a pipeline stall, and second as a thread select signal between threads so that, again, usage of an extra global interconnection between threads for thread selection is avoided. A third thread-switching operation is an “intelligent global scheduler” thread-switching in which a thread switch decision is based on a plurality of signals including: (1) an L1 data cache miss stall signal, (2) an instruction buffer empty signal, (3) an L2 cache miss signal, (4) a thread priority signal, (5) a thread timer signal, (6) an interrupt signal, or other sources of triggering. In some embodiments, the thread select signal is broadcast as fast as possible, similar to a clock tree distribution. In some systems, a processor derives a thread select signal that is applied to the flip-flops by overloading a scan enable (SE) signal of a scannable flip-flop.
    • 处理器包括线程切换控制逻辑,其响应于L1高速缓存未命中而执行快速线程切换操作。 快速线程切换操作实现了几种线程切换方法中的一种或多种。 第一个线程切换操作对于每个N个周期是“忽视的”线程切换,其中各个触发器本地确定线程切换而不通知失速。 遗忘的技术避免了在线程选择的线程之间使用额外的全局互连。 第二个线程切换操作是与现有的“流水线失速”信号(如果有的话)一起使用的“半隐匿”线程切换。 流水线失速信号以两个容量运行,首先作为流水线停顿的通知,第二个作为线程之间的线程选择信号,这样就可以避免线程选择线程之间额外的全局互连使用。 第三线程切换操作是“智能全局调度器”线程切换,其中线程切换决定基于多个信号,包括:(1)L1数据高速缓存未命中停止信号,(2)指令缓冲器空信号 ,(3)L2高速缓存未命中信号,(4)线程优先信号,(5)线程定时器信号,(6)中断信号或其他触发源。 在一些实施例中,类似于时钟树分布,尽可能快地广播线程选择信号。 在一些系统中,处理器通过过载可扫描触发器的扫描使能(SE)信号来导出施加到触发器的线程选择信号。
    • 20. 发明授权
    • System and method for space efficient hashcode allocation
    • 用于空间有效的哈希码分配的系统和方法
    • US06233621B1
    • 2001-05-15
    • US08640245
    • 1996-04-30
    • William N. Joy
    • William N. Joy
    • G06F900
    • G06F9/449G06F12/023Y10S707/99953Y10S707/99957
    • In summary, the present invention is a multithreaded computer system having a memory that stores a plurality of objects and a plurality of procedures. The system uses a first global hashing procedure to service requests for the hashcodes of objects that do not have hashcodes, a local object-specific hashing procedure to service requests for hashcodes that have a recently generated hashcode, and a second global hashing procedure to service requests for the hashcodes of objects that have their hashcodes stored with the object. The global object hashing procedure has instructions for creating for each object a local object-specific hashing procedure. The local object hashing procedure includes as private data a hashcode and instructions for retrieving the hashcode. The second global hashing procedure includes instructions for retrieving the hashcode from the object. A hashcode cleanup procedure, executed during the system's garbage collection process, releases the local object-specific hashing procedure of an object and stores the hashcode with the object.
    • 总之,本发明是具有存储多个对象和多个过程的存储器的多线程计算机系统。 该系统使用第一全局散列过程来服务对不具有哈希码的对象的哈希码的请求,本地特定于对象的散列过程来服务具有最近生成的哈希码的哈希码的请求,以及用于服务请求的第二全局散列过程 对于具有与对象存储的其哈希码的对象的哈希码。 全局对象散列过程具有为每个对象创建本地特定于对象的散列过程的指令。 本地对象散列过程包括作为专用数据的哈希码和用于检索哈希码的指令。 第二个全局散列过程包括从对象中检索哈希码的指令。 在系统的垃圾收集过程中执行的散列码清理过程释放对象的本地特定于对象的哈希过程,并将该哈希码存储在对象中。