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11. 发明授权

US06344651B1 Differential current mode output circuit for electro-optical sensor arrays 有权
标题翻译：差分电流模式输出电路用于电光传感器阵列
公开(公告)号：US06344651B1
公开(公告)日：2002-02-05
申请号：US09427645
申请日：1999-10-27
申请人： James T. Woolaway , William J. Parrish , Stephen H. Black
发明人： James T. Woolaway , William J. Parrish , Stephen H. Black
IPC分类号： H03F345
CPC分类号： G01J5/24 , H03F3/082 , H03F3/45197 , H03F3/68 , H03F2203/45652 , H03F2203/45658 , H03F2203/45682 , H04N5/33
摘要： A differential current mode amplifier circuit (5,5′) includes a first circuit leg having a first current source providing a current I1 coupled in series with a first transistor (m1) at a first circuit node (n1). The first transistor has a control terminal for coupling to an input signal potential (Vs). Vs is obtained from a unit cell of a radiation detector array, and is indicative of a magnitude of an integrated, photon-induced charge. The first circuit leg outputs a first output current (Is). A second circuit leg includes a second current source providing a current I2 coupled in series with a second transistor (m2) at a second circuit node (n2). The second transistor has a control terminal for coupling to an input reference potential (Vr). The second circuit leg outputs a second output current (Ir). A resistance (Rs) is coupled between the first circuit leg and the second circuit leg at the first circuit node and the second node. The current flow through Rs is proportional to a difference between Vs and Vr, and is thus indicative of a magnitude of Vs.
摘要翻译：差分电流模式放大器电路（5,5'）包括具有第一电流源的第一电路支路，该第一电流源提供与第一电路节点（n1）上的第一晶体管（m1）串联耦合的电流I1。第一晶体管具有用于耦合到输入信号电位（Vs）的控制端子。 Vs是从放射线检测器阵列的单位单元获得的，并且表示积分的光子诱导电荷的大小。第一电路支路输出第一输出电流（Is）。第二电路支路包括提供与第二电路节点（n2）上的第二晶体管（m2）串联耦合的电流I2的第二电流源。第二晶体管具有用于耦合到输入参考电位（Vr）的控制端子。第二电路支路输出第二输出电流（Ir）。电阻（Rs）在第一电路节点和第二节点处耦合在第一电路支路和第二电路支路之间。通过Rs的电流与Vs和Vr之间的差成比例，因此表示Vs的大小。

12. 发明授权

US07034301B2 Microbolometer focal plane array systems and methods 有权
标题翻译：微光度计焦平面阵列系统和方法
公开(公告)号：US07034301B2
公开(公告)日：2006-04-25
申请号：US10761769
申请日：2004-01-20
申请人： William J. Parrish , Naseem Y. Aziz , Eric A. Kurth , John D. Schlesselmann
发明人： William J. Parrish , Naseem Y. Aziz , Eric A. Kurth , John D. Schlesselmann
IPC分类号： G01J5/00
CPC分类号： G01J5/22 , G01J5/02 , G01J5/023 , G01J5/20 , G01J5/522 , H04N5/33 , H04N5/361 , H04N5/365
摘要： Systems and methods for microbolometer focal plane arrays are disclosed. For example, in accordance with an embodiment of the present invention, microbolometer focal plane array circuitry is disclosed for a microbolometer array having shared contacts between adjacent microbolometers. Various techniques may be applied to compensate for non-uniformities, such as for example, to allow operation over a calibrated temperature range.
摘要翻译：公开了用于微测光计焦平面阵列的系统和方法。例如，根据本发明的实施例，公开了一种具有在相邻的微测热计之间具有共享触点的微热辐射计阵列的微测热计焦平面阵列电路。可以应用各种技术来补偿不均匀性，例如允许在校准的温度范围上进行操作。

13. 发明授权

US07015715B2 Hybrid gap measurement circuit 有权
标题翻译：混合间隙测量电路
公开(公告)号：US07015715B2
公开(公告)日：2006-03-21
申请号：US10395431
申请日：2003-03-24
申请人： William J. Parrish , Jeffrey B. Barton , Naseem Y. Aziz , Adrienne N. Costello
发明人： William J. Parrish , Jeffrey B. Barton , Naseem Y. Aziz , Adrienne N. Costello
IPC分类号： G01R31/02
CPC分类号： G01B7/14
摘要： Systems and methods are disclosed for measuring a distance (or gap) between substrates of a hybrid semiconductor. The measurements may be made during a hybridization process to, for example, provide alignment feedback during the hybridization process. The measurements may also be made after the hybridization process to further calibrate the process or to provide information useful for further processing operations.
摘要翻译：公开了用于测量混合半导体衬底之间的距离（或间隙）的系统和方法。可以在杂交过程期间进行测量，例如在杂交过程期间提供对准反馈。还可以在杂交过程之后进行测量以进一步校准该过程或提供对进一步处理操作有用的信息。

14. 发明授权

US06550665B1 Method for electrically interconnecting large contact arrays using eutectic alloy bumping 有权
标题翻译：使用共晶合金凸块电连接大型接触阵列的方法
公开(公告)号：US06550665B1
公开(公告)日：2003-04-22
申请号：US09876780
申请日：2001-06-06
申请人： William J. Parrish , Jeffrey B. Barton
发明人： William J. Parrish , Jeffrey B. Barton
IPC分类号： B23K3102
CPC分类号： H01L24/81 , B23K35/26 , H01L21/563 , H01L24/28 , H01L2224/05001 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/05571 , H01L2224/05573 , H01L2224/13109 , H01L2224/13111 , H01L2224/29109 , H01L2224/29111 , H01L2224/2919 , H01L2224/73203 , H01L2224/73204 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01037 , H01L2924/01043 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01055 , H01L2924/01058 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/01327 , H01L2924/0133 , H01L2924/014 , H01L2924/14 , H01L2924/01031 , H01L2924/01083 , H01L2924/00014 , H01L2924/0665
摘要： Methods of forming arrays of electrical interconnects between substrates are provided. These methods allow the use of large interconnect bump arrays to physically and electrically connect substrates without the need to use excess pressure on the substrates to form the interconnects, thus reducing damage to the substrates. To form the interconnects, an array of bumps is formed on a first substrate from a material that forms a eutectic composition with a second material. An array of bumps composed of the second material is formed on the second substrate. The arrays are aligned and the bumps contacted at a temperature above the eutectic temperature of the eutectic composition. Each of the bumps on the first substrate melts and diffuises into the corresponding bumps on the second substrate to form the interconnects.
摘要翻译：提供了在基板之间形成电互连阵列的方法。这些方法允许使用大的互连凸点阵列来物理和电连接衬底，而不需要在衬底上使用过量的压力来形成互连，从而减少对衬底的损伤。为了形成互连，从第二材料形成共晶组合物的材料在第一衬底上形成凸起阵列。由第二材料构成的凸起阵列形成在第二基板上。将阵列对准，并且凸块在高于共晶组成的共晶温度的温度下接触。第一基板上的每个凸起熔化并扩散到第二基板上的相应凸块中以形成互连。

15. 发明授权

US6133596A Near complete charge transfer device 有权
标题翻译：近完全电荷转移装置
公开(公告)号：US6133596A
公开(公告)日：2000-10-17
申请号：US296047
申请日：1999-04-21
申请人： James T. Woolaway , William J. Parrish , Stephen H. Black
发明人： James T. Woolaway , William J. Parrish , Stephen H. Black
IPC分类号： H01L27/146 , H01L29/768 , H01L27/148
CPC分类号： H01L27/146 , H01L29/768
摘要： A charge transfer structure (30) includes a substrate comprised of semiconductor material and, coupled to a surface of the substrate, a plurality of serially coupled devices each having a gate terminal. The plurality of serially coupled devices include a first single port device (D1) defining a first primary charge storage well, a second single port device (D3) defining a second primary charge storage well, a first two port device (D2) defining a first transfer device, a second two port device (D4) defining a second transfer device, and two instances of a third two port device each defining a cascode device (CD). The ports of these devices are serially coupled together in an order given by D1, D2, CD, D3, D4, CD for transferring charge between the first and second primary charge storage wells. Charge is inserted into and withdrawn from each of the first and second primary charge storage wells through a single diffusion that functions as both an input port and an output port. A clock signal (P1) applied to the gate of D1 and a clock signal (P3) applied to the gate of D3 are each predetermined to deplete an underlying surface region of the substrate for forming the first primary charge storage well and the second primary charge storage well, respectively, without requiring the use of diffusion implants as in conventional bucket brigade devices.
摘要翻译：电荷转移结构（30）包括由半导体材料构成的衬底，并且耦合到衬底的表面，每个具有栅极端子的多个串联耦合器件。多个串联耦合器件包括限定第一初级电荷存储阱的第一单端口器件（D1），限定第二电荷存储阱的第二单端口器件（D3），限定第一电荷存储阱传输设备，定义第二传送设备的第二双端口设备（D4）和每个定义共享共享设备（CD）的第三双端口设备的两个实例。这些器件的端口以D1，D2，CD，D3，D4，CD给出的顺序串联在一起，用于在第一和第二主要电荷存储阱之间传送电荷。通过用作输入端口和输出端口的单个扩散器将电荷插入并从每个第一和第二主电荷存储阱中抽出。施加到D1的栅极的时钟信号（P1）和施加到D3的栅极的时钟信号（P3）都被预先设定，以消耗用于形成第一初级电荷存储阱的基板的下表面区域和第二主要电荷存储井，而不需要使用扩散植入物，如在常规斗式装置中。

16. 发明授权

US5084704A Focal plane analog-to-digital converter 失效
标题翻译：焦平面模数转换器
公开(公告)号：US5084704A
公开(公告)日：1992-01-28
申请号：US473742
申请日：1990-02-02
申请人： William J. Parrish
发明人： William J. Parrish
IPC分类号： H03M1/56
CPC分类号： H03M1/56
摘要： An integrated circuit analog-to-digital converter for use on the focal plane of an infrared detector array. The analog-to-digital converter has a sample and hold circuit, a comparator circuit, and a latch circuit. A single slope conversion technique is used to generate digital signals representative of the amplitude of the input analog signal.
摘要翻译：一种用于红外探测器阵列焦平面上的集成电路模数转换器。模数转换器具有采样和保持电路，比较器电路和锁存电路。单斜率转换技术用于产生代表输入模拟信号幅度的数字信号。

17. 发明授权

US4633086A Input circuit for infrared detector 失效
标题翻译：红外探测器输入电路
公开(公告)号：US4633086A
公开(公告)日：1986-12-30
申请号：US721425
申请日：1985-04-09
申请人： William J. Parrish
发明人： William J. Parrish
IPC分类号： H01L27/148 , H01L27/14
CPC分类号： H01L27/14881
摘要： A method and circuit are provided for interfacing an infrared detector to a common power supply and signal processing circuitry. A multichannel input circuit including a plurality of buffer circuits and a common bias network is formed on a single semiconductor substrate. The common bias network reduces the necessary connections between the substrate and the external power supply. The bias network is operative to reduce power level variations in the signal from the external power supply. Each channel includes a negative feedback circuit to maintain a dedicated detector in a zero bias condition, thus reducing 1/f noise and enhancing the signal-to-noise ratio of the circuit. The load to each channel is adjustable to maintain the detector in the zero bias condition.
摘要翻译：提供了用于将红外检测器与公共电源和信号处理电路接口的方法和电路。包括多个缓冲电路和公共偏置网络的多通道输入电路形成在单个半导体衬底上。普通偏置网络减少了基板和外部电源之间的必要连接。偏置网络用于降低来自外部电源的信号的功率电平变化。每个通道包括负反馈电路，以将专用检测器保持在零偏置状态，从而降低1 / f噪声并提高电路的信噪比。每个通道的负载是可调节的，以将检测器保持在零偏置状态。

18. 发明授权

US5053700A Method for wafer scale testing of redundant integrated circuit dies 失效
标题翻译：冗余集成电路管芯晶圆规模测试方法
公开(公告)号：US5053700A
公开(公告)日：1991-10-01
申请号：US532059
申请日：1990-06-01
申请人： William J. Parrish
发明人： William J. Parrish
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G06F11/22 , G06F11/26 , G11C29/00 , H01L21/66
CPC分类号： H01L22/22 , G01R31/2831 , G01R31/31712 , G01R31/31715 , G01R31/318505 , G01R31/318511 , G06F11/26 , G11C29/006 , G06F11/2273 , H01L2924/0002
摘要： A wafer scale test system for testing redundant integrated circuit dies formed on a semiconductor wafer includes wafer scale test pads formed on the wafer and interchip multiplexor means for directing test signals applied to the wafer scale test pads to the individual integrated circuit dies. The interchip multiplexor means includes an input/output buffer circuit for receiving test signals from the wafer pads and applying the test signals to selected interchip multiplexor lines routed to the individual circuit dies. Readouts from output pads on said integrated circuit dies are routed back through the input/output buffer circuit to the wafer test pads to provide test output signals. Low cross-section connecting means are provided across dicing lanes between the integrated circuit die contact pads and the interchip multiplexor lines to avoid shorting during the dicing operation. Additionally, line protection circuits are provided to prevent destruction of the integrated circuit dies should shorting occur during dicing. The integrated circuit dies and wafer scale test system may optionally be partitioned into several separate groups to prevent faults in the interchip multiplexor system from rendering the entire wafer useless.
摘要翻译：用于测试形成在半导体晶片上的冗余集成电路管芯的晶片级测试系统包括晶片上形成的晶片刻度测试焊盘和用于将施加到晶片尺度测试焊盘上的测试信号引导到各个集成电路管芯的芯片间复用器装置。芯片间复用器装置包括用于接收来自晶片焊盘的测试信号的输入/输出缓冲电路，并将测试信号施加到被路由到各个电路管芯的选定的芯片间多路复用器线路。所述集成电路管芯上的输出焊盘的读出通过输入/输出缓冲电路返回到晶片测试焊盘，以提供测试输出信号。在集成电路裸片接触焊盘和芯片间复用器线之间的切割通道之间提供低横截面连接装置，以避免在切割操作期间的短路。此外，提供线路保护电路以防止在切割期间发生短路时集成电路芯片的破坏。集成电路管芯和晶片刻度测试系统可以可选地分成几个单独的组，以防止芯片间复用器系统中的故障使整个晶片无用。

19. 发明授权

US5039879A Digitally programmable gain normalization circuit 失效
标题翻译：数字可编程增益归一化电路
公开(公告)号：US5039879A
公开(公告)日：1991-08-13
申请号：US473835
申请日：1990-02-02
申请人： William J. Parrish
发明人： William J. Parrish
IPC分类号： G11C27/02
CPC分类号： G11C27/024
摘要： A digitally programmable gain normalization circuit for normalizing gains among analog signal channels. The gain normalization circuit is comprised of a charge integrator which has a plurality of capacitors to provide selectible capacitance values which determine the gain of a differential amplifier/sample and hold circuit. A programmable gain control register selects the charge integrator capacitance value. Both static and dynamic latches are disclosed for selecting the capacitors to be utilized in the charge integrator.
摘要翻译：一种数字可编程增益归一化电路，用于对模拟信号通道之间的增益进行归一化。增益归一化电路由具有多个电容器的电荷积分器组成，以提供确定差分放大器/采样和保持电路的增益的可选择的电容值。可编程增益控制寄存器选择电荷积分器电容值。公开静态和动态锁存器用于选择要在电荷积分器中使用的电容器。

20. 发明授权

US07752742B1 Infrared camera packaging 有权
标题翻译：红外相机包装
公开(公告)号：US07752742B1
公开(公告)日：2010-07-13
申请号：US12194461
申请日：2008-08-19
申请人： Paul Schweikert , William J. Parrish , Andrew Sharpe , Vu L. Nguyen , Marco Scussat
发明人： Paul Schweikert , William J. Parrish , Andrew Sharpe , Vu L. Nguyen , Marco Scussat
IPC分类号： B23P19/00
CPC分类号： G01J5/04 , G01J5/045 , G01J2005/0077 , H01L23/10 , H01L23/26 , H01L2924/0002 , H01L2924/01079 , H04N5/33 , Y10T29/4913 , Y10T29/49144 , Y10T29/49169 , Y10T29/53174 , Y10T29/53191 , Y10T29/53261 , H01L2924/00
摘要： Systems and methods for providing a sealed container having a reduced pressure atmosphere are disclosed. The container is suitable for housing an infrared detector array. Outgassing can be enhanced by adding features to solder preforms that maintain pathways for gasses to more readily exit the container prior to sealing thereof. Getters can be used to mitigate undesirable gases within the sealed container. One or more bolometers can be used to determine if the sealed container is leaking. A vacuum positioning fixture can be used to assemble the components of the infrared detector assembly and to place the infrared detector assemblies into a vacuum chamber. The cost of manufacturing such infrared detector assemblies may be reduced and the reliability thereof enhanced.
摘要翻译：公开了一种用于提供具有减压气氛的密封容器的系统和方法。该容器适用于容纳红外探测器阵列。可以通过向焊料预成型件添加特征来增强排气，焊料预成型件在密封之前保持气体的路径更容易地离开容器。吸气剂可用于减轻密封容器内的不良气体。一个或多个辐射热量计可用于确定密封容器是否泄漏。可以使用真空定位夹具来组装红外检测器组件的部件并将红外检测器组件放置在真空室中。可以降低制造这种红外检测器组件的成本，并提高其可靠性。

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