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11. 发明申请

US20090108316A1 MEMORY DEVICE WITH MEMORY CELL INCLUDING MUGFET AND FIN CAPACITOR 有权
标题翻译：具有包含MUGFET和FIN电容器的存储器单元的存储器件
公开(公告)号：US20090108316A1
公开(公告)日：2009-04-30
申请号：US11924817
申请日：2007-10-26
申请人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
发明人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
IPC分类号： H01L29/94
CPC分类号： H01L29/94 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L28/60 , H01L29/785 , H01L29/7855
摘要： One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.
摘要翻译：本发明的一个实施例涉及一种存储单元。存储单元包括与半导体鳍片的第一区域相关联的多栅极场效应晶体管。存储单元还包括耦合到多栅极场效应晶体管的漏极并与半导体鳍片的第二区域相关联的散热片电容器，其中散热片电容器在第二区域中具有大致简并掺杂浓度。还公开了其它装置和方法。

12. 发明授权

US08581317B2 SOI MuGFETs having single gate electrode level 有权
标题翻译：具有单栅电极层的SOI MuGFET
公开(公告)号：US08581317B2
公开(公告)日：2013-11-12
申请号：US12199041
申请日：2008-08-27
申请人： Howard Tigelaar , Cloves Rinn Cleavelin , Andrew Marshall , Weize Xiong
发明人： Howard Tigelaar , Cloves Rinn Cleavelin , Andrew Marshall , Weize Xiong
IPC分类号： H01L27/115
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A silicon on insulator (SOI) multi-gate field effect transistor electrically Programmable Read-Only Memory (MuFET EPROM) includes a substrate having a dielectric surface. A first semiconducting region is in or on the dielectric surface. A source region, a drain region and a channel region interposed between the source and drain are formed in first semiconducting region. A gate dielectric layer is on the channel region. At least a second semiconducting region in or on the dielectric surface is spaced apart from the first semiconducting region. A first electrode layer comprises a first electrode portion including a transistor gate electrode and a control gate electrode electrically isolated from one another. The transistor gate overlies the channel region to form a transistor. The control gate extends to overlay a portion of the second semiconducting region. The transistor gate and thus the transistor and the control gate are capacitively coupled to one another by at least one MOS coupling capacitor, with one plate of the MOS coupling capacitor ohmically coupled to or including the second semiconducting region.
摘要翻译：绝缘体上硅（SOI）多栅极场效应晶体管电可编程只读存储器（MuFET EPROM）包括具有电介质表面的衬底。第一半导电区域位于电介质表面中或其上。源极区域，漏极区域和介于源极和漏极之间的沟道区域形成在第一半导体区域中。栅介质层位于沟道区上。电介质表面中或电介质表面上的至少第二半导体区域与第一半导体区域间隔开。第一电极层包括第一电极部分，其包括晶体管栅电极和彼此电隔离的控制栅电极。晶体管栅极覆盖沟道区以形成晶体管。控制门延伸以覆盖第二半导体区域的一部分。晶体管栅极，因此晶体管和控制栅极通过至少一个MOS耦合电容器彼此电容耦合，MOS耦合电容的一个板欧姆耦合到或包括第二半导体区域。

13. 发明授权

US07939393B2 Method of adjusting FDSOI threshold voltage through oxide charges generation in the buried oxide 有权
标题翻译：通过掩埋氧化物中氧化物电荷产生来调整FDSOI阈值电压的方法
公开(公告)号：US07939393B2
公开(公告)日：2011-05-10
申请号：US12062968
申请日：2008-04-04
申请人： Weize Xiong , Cloves Rinn Cleavelin
发明人： Weize Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L21/337
CPC分类号： H01L21/31155 , H01L21/26506 , H01L21/28211 , H01L21/823842 , H01L21/823878 , H01L21/84
摘要： Different performance MOSFET Fully Depleted devices can be achieved on a single chip by varying the Vt through ion implantation. The integration of multiple Vt can be achieved through the selection of a metal gate stack with suitable effective WF for one semiconductor device to be included on a chip. Then, an ion implantation, with a dopant such as F, can be selectively performed to achieve proper Vt for other semiconductor devices on the chip.
摘要翻译：通过改变Vt通过离子注入，可以在单个芯片上实现不同性能的MOSFET完全耗尽的器件。可以通过选择具有合适的有效WF的金属栅极堆叠来实现多个Vt的集成，一个半导体器件将被包括在芯片上。然后，可以选择性地执行具有诸如F的掺杂剂的离子注入，以为芯片上的其它半导体器件实现适当的Vt。

14. 发明申请

US20080290414A1 INTEGRATING STRAIN ENGINEERING TO MAXIMIZE SYSTEM-ON-A-CHIP PERFORMANCE 审中-公开
标题翻译：集成菌株工程，以最大限度地提高系统级芯片性能
公开(公告)号：US20080290414A1
公开(公告)日：2008-11-27
申请号：US11753241
申请日：2007-05-24
申请人： Weize Xiong , Cloves Rinn Cleavelin
发明人： Weize Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L31/036 , H01L21/336 , H01L27/01
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823842 , H01L27/11 , H01L29/785
摘要： A semiconductor device comprising a first transistor device and second transistor device both on a semiconductor substrate. The first transistor device has a first n-channel and a first p-channel and the second transistor device has a second n-channel and a second p-channel. Each of the p-channels and the n-channels have a long lateral axis that is aligned with a orientation plane of a silicon layer of the semiconductor substrate. The second p-channel and the first and second n-channels include the silicon layer configured as strained silicon. The first p-channel includes the silicon layer configured as relaxed silicon. Each of the n-channels contact gate structures that impart a tensile stress in the n-channels.
摘要翻译：一种半导体器件，包括半导体衬底上的第一晶体管器件和第二晶体管器件。第一晶体管器件具有第一n沟道和第一p沟道，并且第二晶体管器件具有第二n沟道和第二p沟道。 p沟道和n沟道中的每一个具有与半导体衬底的硅层的取向平面对准的长横向轴线。第二p沟道和第一和第二n沟道包括被配置为应变硅的硅层。第一p沟道包括被配置为松弛硅的硅层。 n沟道中的每一个接触在n沟道中赋予拉伸应力的栅极结构。

15. 发明申请

US20080233697A1 Multiple-gate MOSFET device and associated manufacturing methods 有权
标题翻译：多栅MOSFET器件及相关制造方法
公开(公告)号：US20080233697A1
公开(公告)日：2008-09-25
申请号：US11726516
申请日：2007-03-22
申请人： Craig Henry Huffman , Weize Xiong , Cloves Rinn Cleavelin
发明人： Craig Henry Huffman , Weize Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7853
摘要： One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The exposed surface of the first gate electrode material is deglazed. Subsequently, the first gate electrode material is removed. Other methods and devices are also disclosed.
摘要翻译：本发明的一个实施例涉及一种制造多栅极晶体管的方法。在该方法期间，从形成多栅极晶体管的半导体结构中选择性地去除第二栅电极材料，从而暴露第一栅极电极材料的至少一个表面。第一栅电极材料的暴露表面被去角质化。随后，去除第一栅电极材料。还公开了其它方法和装置。

16. 发明申请

US20100052025A1 SOI MUGFETS HAVING SINGLE GATE ELECTRODE LEVEL 有权
标题翻译：具有单门电极水平的SOI MUGFETS
公开(公告)号：US20100052025A1
公开(公告)日：2010-03-04
申请号：US12199041
申请日：2008-08-27
申请人： Howard Lee Tigelaar , Cloves Rinn Cleavelin , Andrew Marshall , Weize Xiong
发明人： Howard Lee Tigelaar , Cloves Rinn Cleavelin , Andrew Marshall , Weize Xiong
IPC分类号： H01L27/115
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A silicon on insulator (SOI) multi-gate field effect transistor electrically Programmable Read-Only Memory (MuFET EPROM) includes a substrate having a dielectric surface. A first semiconducting region is in or on the dielectric surface. A source region, a drain region and a channel region interposed between the source and drain are formed in first semiconducting region. A gate dielectric layer is on the channel region. At least a second semiconducting region in or on the dielectric surface is spaced apart from the first semiconducting region. A first electrode layer comprises a first electrode portion including a transistor gate electrode and a control gate electrode electrically isolated from one another. The transistor gate overlies the channel region to form a transistor. The control gate extends to overlay a portion of the second semiconducting region. The transistor gate and thus the transistor and the control gate are capacitively coupled to one another by at least one MOS coupling capacitor, with one plate of the MOS coupling capacitor ohmically coupled to or including the second semiconducting region.
摘要翻译：绝缘体上硅（SOI）多栅极场效应晶体管电可编程只读存储器（MuFET EPROM）包括具有电介质表面的衬底。第一半导电区域位于电介质表面中或其上。源极区域，漏极区域和介于源极和漏极之间的沟道区域形成在第一半导体区域中。栅介质层位于沟道区上。电介质表面中或电介质表面上的至少第二半导体区域与第一半导体区域间隔开。第一电极层包括第一电极部分，其包括晶体管栅电极和彼此电隔离的控制栅电极。晶体管栅极覆盖沟道区以形成晶体管。控制门延伸以覆盖第二半导体区域的一部分。晶体管栅极，因此晶体管和控制栅极通过至少一个MOS耦合电容器彼此电容耦合，MOS耦合电容的一个板欧姆耦合到或包括第二半导体区域。

17. 发明申请

US20100002494A1 Memory Device with Memory Cell Including MuGFET and FIN Capacitor 有权
标题翻译：具有包含MuGFET和FIN电容器的存储单元的存储器件
公开(公告)号：US20100002494A1
公开(公告)日：2010-01-07
申请号：US12554660
申请日：2009-09-04
申请人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
发明人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
IPC分类号： G11C11/24 , H01L27/108 , G11C7/00
CPC分类号： H01L29/94 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L28/60 , H01L29/785 , H01L29/7855
摘要： One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.
摘要翻译：本发明的一个实施例涉及一种存储单元。存储单元包括与半导体鳍片的第一区域相关联的多栅极场效应晶体管。存储单元还包括耦合到多栅极场效应晶体管的漏极并与半导体鳍片的第二区域相关联的散热片电容器，其中散热片电容器在第二区域中具有大致简并掺杂浓度。还公开了其它装置和方法。

18. 发明授权

US07122442B2 Method and system for dopant containment 有权
公开(公告)号：US07122442B2
公开(公告)日：2006-10-17
申请号：US10897634
申请日：2004-07-22
申请人： Cloves Rinn Cleavelin
发明人： Cloves Rinn Cleavelin
IPC分类号： H01L21/76
CPC分类号： H01L21/26506 , H01L21/76254 , H01L29/7833
摘要： According to one embodiment, a semiconductor device is provided. The semiconductor device includes an oxide layer. The semiconductor device also includes a silicon layer disposed outwardly from the oxide layer and having at least one region comprising a dopant. The semiconductor device also includes a dielectric layer disposed outwardly from the silicon layer. The semiconductor device also includes a gate disposed outwardly from the dielectric layer. The semiconductor device also includes a blocking layer disposed between the oxide layer and the silicon layer. The blocking layer is operable to at least partially block a transfer of the dopant from the at least one region of the silicon layer to the oxide layer.

19. 发明授权

US6097296A Apparatus and method for detecting tornadoes 失效
标题翻译：检测龙卷风的装置及方法
公开(公告)号：US6097296A
公开(公告)日：2000-08-01
申请号：US138937
申请日：1998-08-24
申请人： Santos Garza , Cloves Rinn Cleavelin
发明人： Santos Garza , Cloves Rinn Cleavelin
IPC分类号： G01W1/00
CPC分类号： G01W1/00
摘要： A tornado detector comprising a sensor (30) for sensing the presence of sound having a frequency of about one hertz and for providing a sound sense signal in response thereto, a filter (50) to attenuate said sound sense signal wave components having frequencies greater than those which correspond to sound having a frequency of about one hertz, and an alarm (101) for generating an alarm signal in response to said filtered sound sense signal.
摘要翻译：一种龙卷风检测器，包括用于感测具有大约1赫兹频率的声音的传感器的传感器（30），并且用于响应于此提供声音感测信号;滤波器（50），用于衰减所述声音感测信号波分量的频率大于对应于具有大约1赫兹频率的声音的那些，以及用于响应于所述滤波的声音感测信号产生报警信号的报警器（101）。

20. 发明授权

US07638843B2 Integrating high performance and low power multi-gate devices 有权
标题翻译：集成高性能和低功耗多栅极器件
公开(公告)号：US07638843B2
公开(公告)日：2009-12-29
申请号：US11381888
申请日：2006-05-05
申请人： Weize W. Xiong , Cloves Rinn Cleavelin
发明人： Weize W. Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L29/76 , H01L29/94
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A semiconductor device comprises a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprises a first gate structure and the second multi-gate device comprises a second gate structure. An effective width of the first gate structure is greater than an effective width of the second gate structure.
摘要翻译：半导体器件包括半导体衬底上的第一多栅极器件和第二多栅极器件。第一多栅极器件包括第一栅极结构，第二多栅极器件包括第二栅极结构。第一栅极结构的有效宽度大于第二栅极结构的有效宽度。

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