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11. 发明申请

US20130262775A1 Cache Management for Memory Operations 有权
标题翻译：内存操作缓存管理
公开(公告)号：US20130262775A1
公开(公告)日：2013-10-03
申请号：US13436767
申请日：2012-03-30
申请人： Anthony ASARO , Kevin Normoyle , Mark Hummel , Norman Rubin , Mark Fowler
发明人： Anthony ASARO , Kevin Normoyle , Mark Hummel , Norman Rubin , Mark Fowler
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0815 , G06F12/0837 , G06F12/0877 , G06F12/123 , G06F12/126 , G06F12/128
摘要： Embodiments of the present invention provides for the execution of threads and/or workitems on multiple processors of a heterogeneous computing system in a manner that they can share data correctly and efficiently. Disclosed method, system, and article of manufacture embodiments include, responsive to an instruction from a sequence of instructions of a work-item, determining an ordering of visibility to other work-items of one or more other data items in relation to a particular data item, and performing at least one cache operation upon at least one of the particular data item or the other data items present in any one or more cache memories in accordance with the determined ordering. The semantics of the instruction includes a memory operation upon the particular data item.
摘要翻译：本发明的实施例提供在异构计算系统的多个处理器上执行线程和/或工作项，以使得它们可以正确且有效地共享数据。公开的方法，系统和制品实施例包括响应于来自工作项目的指令序列的指令，确定与特定数据相关的一个或多个其他数据项的其他工作项的可见性的排序并且根据所确定的顺序对存在于任何一个或多个高速缓存存储器中的特定数据项或其他数据项中的至少一个执行至少一个高速缓存操作。指令的语义包括对特定数据项的存储器操作。

12. 发明申请

US20070038839A1 Controlling an I/O MMU 有权
标题翻译：控制I / O MMU
公开(公告)号：US20070038839A1
公开(公告)日：2007-02-15
申请号：US11503390
申请日：2006-08-11
申请人： Mark Hummel , Andrew Lueck , Geoffrey Strongin , Mitchell Alsup , Michael Haertel
发明人： Mark Hummel , Andrew Lueck , Geoffrey Strongin , Mitchell Alsup , Michael Haertel
IPC分类号： G06F12/00
CPC分类号： G06F12/1081 , G06F12/1027 , G06F12/145
摘要： In an embodiment, a computer system comprises a processor; a memory management module comprising a plurality of instructions executable on the processor; a memory coupled to the processor; and an input/output memory management unit (IOMMU) coupled to the memory. The IOMMU is configured to implement address translation and memory protection for memory operations sourced by one or more input/output (I/O) devices. The memory stores a command queue during use. The memory management module is configured to write one or more control commands to the command queue, and the IOMMU is configured to read the control commands from the command queue and execute the control commands.
摘要翻译：在一个实施例中，计算机系统包括处理器; 存储器管理模块，包括可在所述处理器上执行的多个指令; 耦合到处理器的存储器; 以及耦合到存储器的输入/输出存储器管理单元（IOMMU）。 IOMMU被配置为对由一个或多个输入/输出（I / O）设备提供的存储器操作实现地址转换和存储器保护。内存在使用过程中存储命令队列。存储器管理模块被配置为将一个或多个控制命令写入命令队列，并且IOMMU被配置为从命令队列读取控制命令并执行控制命令。

13. 发明授权

US08879301B2 Method and apparatus for controlling state information retention in an apparatus 有权
标题翻译：用于控制装置中的状态信息保持的方法和装置
公开(公告)号：US08879301B2
公开(公告)日：2014-11-04
申请号：US13616142
申请日：2012-09-14
申请人： David Mayhew , Mark Hummel , Michael Ignatowski
发明人： David Mayhew , Mark Hummel , Michael Ignatowski
IPC分类号： G11C11/00 , G11C13/00 , G11C14/00 , H03K19/00 , G11C11/412 , G11C5/00
CPC分类号： G11C13/0002 , G11C5/005 , G11C11/4125 , G11C14/0045 , H03K19/0016 , H03K19/0019
摘要： A method and apparatus for controlling state information retention determines at least a state information save or restore condition for at least one processing circuit such as one or more CPU or GPU cores or pipelines, in an integrated circuit. In response to determining the state information save or restore condition, the method and apparatus controls either or both of saving or restoring of state information for different virtual machines operating on the processing circuit, into corresponding on-die persistent passive variable resistance memory. The state information save or restore condition is a virtual machine level state information save or restore condition. State information for each of differing virtual machines is saved or restored from differing on-die passive variable resistance memory cells that are assigned on a per-virtual machine basis.
摘要翻译：用于控制状态信息保持的方法和装置至少确定集成电路中至少一个处理电路（例如一个或多个CPU或GPU核心或管线）的状态信息保存或恢复条件。响应于确定状态信息保存或恢复条件，该方法和装置控制将处理电路上运行的不同虚拟机的状态信息的保存或恢复中的任一个或两者转换为相应的裸片上持续的可变电阻存储器。状态信息保存或恢复条件是虚拟机级状态信息保存或恢复条件。每个不同虚拟机的状态信息由在每个虚拟机基础上分配的不同的片上可变电阻存储器单元进行保存或恢复。

14. 发明申请

US20140068088A1 SYSTEMS AND METHODS FOR PROCESSING MEDIA ACCESS CONTROL (MAC) ADDRESSES 审中-公开
标题翻译：用于处理媒体访问控制（MAC）地址的系统和方法
公开(公告)号：US20140068088A1
公开(公告)日：2014-03-06
申请号：US13602512
申请日：2012-09-04
申请人： Venkata S. Krishnan , Anton Chernoff , Mark Hummel , David E. Mayhew
发明人： Venkata S. Krishnan , Anton Chernoff , Mark Hummel , David E. Mayhew
IPC分类号： G06F15/16
CPC分类号： H04L61/6022 , H04L61/2038
摘要： Described are a system and method for processing a media access control (MAC) address. A communication is established between a processing device and a network port of a data switching device. The data switching device assigns a MAC address to the processing device. The assigned MAC address is directly associated with the network port of the data switching device absent a learning mechanism.
摘要翻译：描述了用于处理媒体访问控制（MAC）地址的系统和方法。在数据交换设备的处理设备和网络端口之间建立通信。数据交换设备向处理设备分配MAC地址。分配的MAC地址与没有学习机制的数据交换设备的网络端口直接相关联。

15. 发明申请

US20140059160A1 SYSTEMS AND METHODS FOR SHARING DEVICES IN A VIRTUALIZATION ENVIRONMENT 有权
标题翻译：在虚拟化环境中共享设备的系统和方法
公开(公告)号：US20140059160A1
公开(公告)日：2014-02-27
申请号：US13590700
申请日：2012-08-21
申请人： Anton Chernoff , Venkata S. Krishnan , Mark Hummel , David E. Mayhew , Michael J. Osborn
发明人： Anton Chernoff , Venkata S. Krishnan , Mark Hummel , David E. Mayhew , Michael J. Osborn
IPC分类号： G06F15/173 , G06F15/16
CPC分类号： H04L49/70 , G06F9/45558 , G06F2009/45579 , H04L49/356
摘要： Described are systems and methods for communication between a plurality of electronic devices and an aggregation device. An aggregation device processes instructions related to a configuration of an electronic device in communication with the aggregation device. One or more virtual devices are generated in response to processing the instructions. The electronic device enumerates a configuration space to determine devices for use by the electronic device. The aggregation device detects an access of the configuration space by the electronic device. The one or more virtual devices are presented from the aggregation device to the electronic device in accordance with the instructions.
摘要翻译：描述了用于多个电子设备和聚合设备之间的通信的系统和方法。聚合设备处理与聚合设备通信的电子设备的配置相关的指令。响应于处理指令而产生一个或多个虚拟设备。电子设备列举配置空间以确定电子设备使用的设备。聚合设备检测电子设备对配置空间的访问。一个或多个虚拟设备根据指令从聚合设备呈现给电子设备。

16. 发明申请

US20130145051A1 Direct Device Assignment 审中-公开
标题翻译：直接设备分配
公开(公告)号：US20130145051A1
公开(公告)日：2013-06-06
申请号：US13309738
申请日：2011-12-02
申请人： Andrew Kegel , Mark Hummel
发明人： Andrew Kegel , Mark Hummel
IPC分类号： G06F3/00
CPC分类号： G06F13/28 , G06F12/1081 , G06F2212/151 , G06F2213/0058
摘要： A system is enabled for configuring an IOMMU to provide direct access to system memory data by at least one I/O device/peripheral. Further, the IOMMU is configured to pass a pointer to at least one I/O device without having to translate the pointer. Further, commands are sent from a process within a guest operating system (OS) directly to a peripheral without intervention from a hypervisor. Further, the IOMMU is configured to grant peripherals access permissions to memory blocks to maintain isolation among peripherals.
摘要翻译：启用一个系统来配置IOMMU以通过至少一个I / O设备/外围设备直接访问系统内存数据。此外，IOMMU被配置为将指针传递到至少一个I / O设备，而不必转换指针。此外，命令从客户操作系统（OS）中的进程直接发送到外设，而无需管理程序的干预。此外，IOMMU被配置为允许外设对存储器块的访问权限，以保持外设之间的隔离。

17. 发明申请

US20120159039A1 Generalized Control Registers 有权
标题翻译：广义控制寄存器
公开(公告)号：US20120159039A1
公开(公告)日：2012-06-21
申请号：US13309748
申请日：2011-12-02
申请人： Andy Kegel , Mark Hummel , Tony Asaro , Philip Ng
发明人： Andy Kegel , Mark Hummel , Tony Asaro , Philip Ng
IPC分类号： G06F12/10
CPC分类号： G06F12/1081 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/151 , Y02D10/13
摘要： Methods, systems, and computer readable media generalize control registers in the context of memory address translations for I/O devices. A method includes maintaining a table including a plurality of concurrently available control register base pointers each associated with a corresponding input/output (I/O) device, associating each control register base pointer with a first translation from a guest virtual address (GVA) to a guest physical address (GPA) and a second translation from the GPA to a system physical address (SPA), and operating the first and second translations concurrently for the plurality of I/O devices.
摘要翻译：在I / O设备的存储器地址转换的上下文中，方法，系统和计算机可读介质泛化控制寄存器。一种方法包括维护包括多个同时可用的控制寄存器基本指针的表，每个与相应的输入/输出（I / O）设备相关联的表，将每个控制寄存器基本指针与来自虚拟地址（GVA）的第一个转换相关联，客户物理地址（GPA）和从GPA到系统物理地址（SPA）的第二翻译，以及为多个I / O设备同时操作第一和第二翻译。

18. 发明申请

US20110202724A1 IOMMU Architected TLB Support 有权
标题翻译： IOMMU架构的TLB支持
公开(公告)号：US20110202724A1
公开(公告)日：2011-08-18
申请号：US12707341
申请日：2010-02-17
申请人： Andrew G. KEGEL , Mark Hummel , Erich Boleyn
发明人： Andrew G. KEGEL , Mark Hummel , Erich Boleyn
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F12/1081 , G06F12/1027 , G06F2212/6028 , G06F2212/654
摘要： Embodiments allow a smaller, simpler hardware implementation of an input/output memory management unit (IOMMU) having improved translation behavior that is independent of page table structures and formats. Embodiments also provide device-independent structures and methods of implementation, allowing greater generality of software (fewer specific software versions, in turn reducing development costs).
摘要翻译：实施例允许具有独立于页表结构和格式的改进的翻译行为的输入/输出存储器管理单元（IOMMU）的更小，更简单的硬件实现。实施例还提供了与设备无关的结构和实现方法，允许更大程度的软件通用性（较少的特定软件版本，从而降低开发成本）。

19. 发明授权

US09253287B2 Speculation based approach for reliable message communications 有权
标题翻译：基于投机的方法可靠的消息通信
公开(公告)号：US09253287B2
公开(公告)日：2016-02-02
申请号：US13589463
申请日：2012-08-20
申请人： Venkata S. Krishnan , Mark Hummel , David E. Mayhew
发明人： Venkata S. Krishnan , Mark Hummel , David E. Mayhew
IPC分类号： G06F15/16 , H04L29/06
CPC分类号： H04L67/40
摘要： Described are a system and method for lossless message delivery between two processing devices. Each device includes a remote direct memory access (RDMA) messaging interface. The RDMA messaging interface at the first device generates one or more messages that are processed by the RDMA messaging interface of the second device. The RDMA messaging interface of the first device outputs a notification to the second device that a message of the one or more messages is available at the first device. A determination is made that the second device has resources to accommodate the message. The second device performs an operation in response to determining that the processing device has the resources to accommodate the message.
摘要翻译：描述了用于两个处理设备之间无损消息传递的系统和方法。每个设备包括远程直接内存访问（RDMA）消息接口。第一设备上的RDMA消息接口生成由第二设备的RDMA消息接发处理的一个或多个消息。第一设备的RDMA消息接口向第二设备输出一个或多个消息的消息在第一设备可用的通知。确定第二设备具有容纳消息的资源。第二装置响应于确定处理装置具有容纳消息的资源而执行操作。

20. 发明授权

US09176794B2 Graphics compute process scheduling 有权
标题翻译：图形计算过程调度
公开(公告)号：US09176794B2
公开(公告)日：2015-11-03
申请号：US13289260
申请日：2011-11-04
申请人： Jeffrey Gongxian Cheng , Paul Blinzer , Mark Hummel , Leendert Peter Van Doorn
发明人： Jeffrey Gongxian Cheng , Paul Blinzer , Mark Hummel , Leendert Peter Van Doorn
IPC分类号： G06F12/02 , G06T1/00 , G06T15/00 , G06F9/54
CPC分类号： G06F9/545 , G06F2209/509
摘要： A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于提供对用户模式应用的加速处理设备计算资源的改进访问。所公开的功能允许用户模式应用程序向加速处理设备提供命令，而不需要内核模式转换以便访问统一的环形缓冲区。相反，应用程序各自提供有自己的缓冲区，加速处理设备硬件可以访问进程命令。通过完整的操作系统支持，用户模式应用程序能够以与CPU相同的方式利用加速处理设备。

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