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11. 发明授权

US5915126A Computer system memory controller and method of burst data ordering translation 失效
标题翻译：计算机系统存储器控制器和突发数据排序转换方法
公开(公告)号：US5915126A
公开(公告)日：1999-06-22
申请号：US909930
申请日：1997-08-12
申请人： Warren Edward Maule , David W. Victor
发明人： Warren Edward Maule , David W. Victor
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A computer system including a memory controller programmed with associated burst order translation logic and coupled to one or more microprocessors and including a memory circuit which supports either sequential or interleaved transmission of burst data communication between an I/O devices and one or more of the microprocessors. Data transmitted to or from an I/O device, processor or memory is temporarily stored in a buffer within the memory controller. The buffers contain multiple addresses with each address capable of containing a quadword of data. The quadwords of data are transferred to the addresses corresponding to which quadword is the requested quadword from the processor. The quadwords are transmitted, requested quadword first then the next quadword, continuing until all quadwords are transmitted. The corresponding addresses are determined through incrementing or decrementing a pointer to the corresponding addresses, dependent upon the burst ordering translation required.
摘要翻译：一种包括存储器控制器的计算机系统，所述存储器控制器被编程有关联的突发命令转换逻辑并且耦合到一个或多个微处理器，并且包括存储器电路，其支持I / O设备与一个或多个微处理器之间的突发数据通信的顺序或交错传输。传输到I / O设备，处理器或存储器的数据被临时存储在存储器控制器内的缓冲器中。缓冲区包含多个地址，每个地址能够包含四字数据。数据的四字被传送到对应于哪个四字是来自处理器的请求的四字的地址。发送四个字，首先要求四字，然后是下一个四字，继续直到所有的四字被发送。取决于所需的突发排序转换，相应的地址通过将指针递增或递减到对应的地址来确定。

12. 发明授权

US5898896A Method and apparatus for data ordering of I/O transfers in Bi-modal Endian PowerPC systems 失效
标题翻译：用于双模式Endian PowerPC系统中I / O传输的数据排序的方法和装置
公开(公告)号：US5898896A
公开(公告)日：1999-04-27
申请号：US826853
申请日：1997-04-10
申请人： John Michael Kaiser , Warren Edward Maule , Robert Dominick Mirabella , David Wayne Victor
发明人： John Michael Kaiser , Warren Edward Maule , Robert Dominick Mirabella , David Wayne Victor
IPC分类号： G06F12/04 , G06F5/00 , G06F7/76 , G06F13/40 , G06F13/38
CPC分类号： G06F7/768 , G06F13/4013
摘要： To present a consistent image of storage facilities to components in Bi-modal Endian PowerPC system enviromnents, provision is made for transferring data between system components in the appropriate Endian format. Endian conversion function can be incorporated into the memory controller subsystem by adding byte-lane swapping logic on the inbound and outbound I/O data paths. With this structure, inbound data from the processor and memory bus will be converted to true Little Endian order before being sent to I/O devices. Likewise, true Little Endian data from I/O devices targeted for the processor or memory is modified to reflect the PowerPC Little Endian byte ordering convention.
摘要翻译：为了向双模态Endian PowerPC系统环境中的组件呈现存储设施的一致形象，提供了以适当的Endian格式在系统组件之间传输数据。通过在入站和出站I / O数据路径中添加字节通道交换逻辑，可以将端序转换功能并入内存控制器子系统。利用这种结构，在发送到I / O设备之前，来自处理器和存储器总线的入站数据将被转换为真正的小端序。同样，针对处理器或内存的I / O设备的真实小端数据也会被修改，以反映PowerPC小端字节排序规则。

13. 发明授权

US5784710A Process and apparatus for address extension 失效
标题翻译：地址扩展的过程和设备
公开(公告)号：US5784710A
公开(公告)日：1998-07-21
申请号：US536808
申请日：1995-09-29
申请人： John Michael Kaiser , Warren Edward Maule
发明人： John Michael Kaiser , Warren Edward Maule
IPC分类号： G06F12/02 , G06F12/06 , G06F12/00
CPC分类号： G06F12/0623
摘要： Circuitry within a system memory controller of a data processing system enables an M-bit processor to address a memory location that requires an N-bit address, wherein N is greater than M. Thus, a less than 48-bit processor will be able to access IPL code resident within a 48-bit memory system. An M-bit address is received from a processor and then extended into an N-bit address with a mask of N-M bits. The extended address is compared with an N-bit address representing the memory location to be addressed, and the extended address is then selected to access the memory location when the extended address equals the N-bit address representing the memory location.
摘要翻译：在数据处理系统的系统存储器控制器内的电路使得M位处理器能够寻址需要N位地址的存储器位置，其中N大于M.因此，小于48位处理器将能够访问驻留在48位内存系统中的IPL代码。从处理器接收M位地址，然后扩展成具有N-M位掩码的N位地址。将扩展地址与表示要寻址的存储器位置的N位地址进行比较，然后当扩展地址等于表示存储器位置的N位地址时，扩展地址被选择以访问存储器位置。

14. 发明授权

US5713029A Information handling system including doze mode control 失效
标题翻译：信息处理系统包括打盹模式控制
公开(公告)号：US5713029A
公开(公告)日：1998-01-27
申请号：US537180
申请日：1995-09-29
申请人： John Michael Kaiser , Warren Edward Maule
发明人： John Michael Kaiser , Warren Edward Maule
IPC分类号： G06F1/32 , G06F13/36
CPC分类号： G06F1/3203 , G06F13/364
摘要： An information handling system includes a system memory controller having a control register in which a bit is reserved for Doze mode control. The Doze control bit is set by system software whenever it places any processor into Doze mode. Until this bit is set, there is no wake up signal issued nor any performance lost. Whenever this control bit is set, the memory controller sends a signal to the system arbiter that informs it to issue a "wake up signal" before issuing an address bus grant, in time to satisfy the processor wake up latency. In addition, if the system arbiter receives another address bus request within a predefined time window, the "wake up signal" is held active without adding to the bus grant latency. If maximum system performance is desired (all processors out of Doze mode), the system software resets the Doze mode control bit in the memory controller, which removes the signal to the system arbiter which controls the wake up signal and removes the added latency for granting the bus.
摘要翻译：一种信息处理系统，包括具有控制寄存器的系统存储器控制器，其中一位被保留用于打盹模式控制。只要将任何处理器置于Doze模式，Doze控制位由系统软件设置。直到这个位被设置，没有发出唤醒信号，也没有任何性能损失。无论何时设置该控制位，存储器控制器向系统仲裁器发送信号，通知它在发出地址总线授权之前发出“唤醒信号”，以及时满足处理器唤醒延迟。另外，如果系统仲裁器在预定义的时间窗口内接收到另一个地址总线请求，则“唤醒信号”保持有效，而不会增加总线授权等待时间。如果需要最大系统性能（Doze模式下的所有处理器），系统软件会重置存储器控制器中的Doze模式控制位，从而将该信号移除到控制唤醒信号的系统仲裁器，并消除额外的延迟延迟公交车。

15. 发明授权

US07373471B2 Executing background writes to idle DIMMs 失效
标题翻译：执行后台写入空闲DIMM
公开(公告)号：US07373471B2
公开(公告)日：2008-05-13
申请号：US11054447
申请日：2005-02-09
申请人： Mark Andrew Brittain , Warren Edward Maule , Gary Alan Morrison , Jeffrey Adam Stuecheli
发明人： Mark Andrew Brittain , Warren Edward Maule , Gary Alan Morrison , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F13/1626
摘要： Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.
摘要翻译：内存模块设计有多个写入缓冲器，用于临时保存写入数据。 “写入缓冲”操作将内存控制器中的写入数据移动到写入缓冲区，同时内存模块正忙于处理读取操作。然后，随后发出仅地址的“写入”命令来将缓冲的写入数据写入存储器件。针对闲置DIMM的写命令在针对繁忙DIMM（或即将忙于）的写入之前按顺序发出。通过后台写入缓冲操作移动数据可以提高通用写入数据通道的效率，并允许写入数据总线在重读操作期间达到最大带宽。实际写入操作，延迟到写入负面影响的时期可以完全/大部分隐藏。在光读取活动期间，或者当没有读取待处理时，缓冲存储器模块中的数据使缓冲数据能够同时跨多个存储器模块并行编写。

16. 发明授权

US06675270B2 Dram with memory independent burst lengths for reads versus writes 有权
标题翻译：具有与存储器无关的突发长度的读取与写入
公开(公告)号：US06675270B2
公开(公告)日：2004-01-06
申请号：US09843060
申请日：2001-04-26
申请人： Ravi Kumar Arimilli , Warren Edward Maule
发明人： Ravi Kumar Arimilli , Warren Edward Maule
IPC分类号： G06F1300
CPC分类号： G06F13/161
摘要： A method and system that enables independent burst lengths for reads and writes to a DRAM subsystem. Specifically, the method provides a mechanism by which read bursts may be longer than write bursts since there are statistically more reads than writes to the DRAM and only some beats of read data are modified and need to be re-written to memory. In the preferred embodiment, the differences in the burst length is controlled by an architected address tenure, i.e., a set of bits added to the read and write commands that specify the specific number of beats to read and/or write. The bits are set by the processor during generation of the read and write commands and prior to forwarding the commands to the memory controller for execution.
摘要翻译：一种能够独立突发长度读取和写入DRAM子系统的方法和系统。具体地说，该方法提供了一种机制，读脉冲串可能比写入脉冲串长，因为统计上读写数据多于写入DRAM，并且仅读取数据的一些节拍被修改并需要重新写入存储器。在优选实施例中，突发长度的差异由架构地址保留权控制，即，添加到指定读取和/或写入的特定次数的读取和写入命令的一组位。这些位在生成读取和写入命令期间以及在将命令转发到存储器控制器以执行之前由处理器设置。

17. 发明授权

US06622222B2 Sequencing data on a shared data bus via a memory buffer to prevent data overlap during multiple memory read operations 有权
标题翻译：通过存储器缓冲器对共享数据总线上的数据进行排序，以防止在多个存储器读取操作期间的数据重叠
公开(公告)号：US06622222B2
公开(公告)日：2003-09-16
申请号：US09843071
申请日：2001-04-26
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Warren Edward Maule
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Warren Edward Maule
IPC分类号： G06F1300
CPC分类号： G06F13/161
摘要： Disclosed is a method and memory subsystem that allows for speculative issuance of reads to a DRAM array to provide efficient utilization of the data out bus and faster read response for accesses to a single DRAM array. Two read requests are issued simultaneously to a first and second DRAM in the memory subsystem, respectively. Data issued from the first DRAM is immediately placed on the data out bus, while data issued from the second DRAM is held in an associated buffer. The processor or memory controller then generates a release signal if the second read is not speculative or is correctly speculated. The release signal is sent to the second DRAM after the first issued data is placed on the bus. The release signal releases the data held in the buffer associated with the second DRAM from the buffer to the data out bus. Because the data has already been issued when the release signal is received, no loss of time is incurred in issuing the data from the DRAM and only a small clock cycle delay occurs between the first issued data and the second issued data on the data out bus.
摘要翻译：公开了一种方法和存储器子系统，其允许对DRAM阵列的读取的推测性发布以提供数据输出总线的有效利用和对单个DRAM阵列的访问的更快的读取响应。两个读取请求分别同时发送到存储器子系统中的第一和第二DRAM。从第一DRAM发出的数据立即被放置在数据输出总线上，而从第二DRAM发出的数据保持在相关的缓冲器中。如果第二次读取不是推测性的或者被正确推测，则处理器或存储器控制器然后产生释放信号。在第一个发布的数据放在总线上之后，释放信号被发送到第二个DRAM。释放信号将保存在与第二DRAM相关联的缓冲器中的数据从缓冲器释放到数据输出总线。由于在接收到释放信号时已经发出数据，所以在从DRAM发出数据时不会发生时间损失，并且在数据总线上的第一次发布的数据和第二个发出的数据之间只发生小的时钟周期延迟。

18. 发明授权

US06581116B1 Method and apparatus for high performance transmission of ordered packets on a bus within a data processing system 失效
标题翻译：用于在数据处理系统内的总线上有序分组的高性能传输的方法和装置
公开(公告)号：US06581116B1
公开(公告)日：2003-06-17
申请号：US09437042
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Vicente Enrique Chung , Warren Edward Maule
发明人： Ravi Kumar Arimilli , Vicente Enrique Chung , Warren Edward Maule
IPC分类号： G06F1300
CPC分类号： G06F13/4269
摘要： A method for transmitting ordered packets on a bus within a data processing system is disclosed. A data processing system includes a bus connected between a bus master and a bus slave. The bus master consecutively issues multiple packets, such as command packets, to the bus slave on the bus. The packets include order sensitive packets and non-order sensitive packets. In response to a temporary inability of the bus slave to process a particular one of the order sensitive packets due to a lack of resources, the bus slave keeps retrying the particular order sensitive packet. When resources become available, the bus slave processes the retried order sensitive packets in order while allowing the retried non-order sensitive packets to be processed in any order.
摘要翻译：公开了一种用于在数据处理系统内的总线上发送有序分组的方法。数据处理系统包括连接在总线主机和总线从机之间的总线。总线主机在总线上连续向总线从站发出多个数据包，如命令数据包。数据包包括顺序敏感数据包和非顺序敏感数据包。由于总线从属单元由于缺乏资源而暂时无法处理特定的一个敏感数据包，所以总线从站不断重试特定的顺序敏感数据包。当资源变得可用时，总线从站按顺序处理重试顺序敏感数据包，同时允许以任何顺序处理重试的非顺序敏感数据包。

19. 发明授权

US5949272A Bidirectional off-chip driver with receiver bypass 失效
标题翻译：带接收器旁路的双向片外驱动器
公开(公告)号：US5949272A
公开(公告)日：1999-09-07
申请号：US873830
申请日：1997-06-12
申请人： Harry Randall Bickford , Paul William Coteus , Warren Edward Maule , Robert Dominick Mirabella
发明人： Harry Randall Bickford , Paul William Coteus , Warren Edward Maule , Robert Dominick Mirabella
IPC分类号： H03K19/0185 , H03K17/62
CPC分类号： H03K19/018592 , H03K19/018585
摘要： A method and apparatus are provided which are implemented in a chip I/O buffer-multiplexor circuit or I/O buffer cell 201. The I/O buffer portion includes a receiver circuit 205 for receiving bus input signals to the buffered chip, and a driver circuit 203 for driving output signals from the buffered chip to a data bus. An integrated multiplexor or MUX circuit 207 selectively gates one of three possible signals to chip internal logic. The three signals applied to the MUX circuit include a boundary scan test signal BS MUX for testing scan points in an integrated circuit, a bypass Data In signal DI which is generated by chip internal drive logic, and a DQ signal received by the I/O buffer receiver circuit from a data bus. The data input node of the I/O buffer is wired directly to the new multiplexor data input. Additional control signals are provided for orthogonal selection of the three multiplexor data inputs.
摘要翻译：提供了一种在芯片I / O缓冲多路复用器电路或I / O缓冲器单元201中实现的方法和装置.I / O缓冲器部分包括用于接收到缓冲芯片的总线输入信号的接收机电路205和用于驱动从缓冲芯片到数据总线的输出信号的驱动器电路203。集成多路复用器或MUX电路207有选择地将三个可能的信号之一门控到芯片内部逻辑。施加到MUX电路的三个信号包括用于测试集成电路中的扫描点的边界扫描测试信号BS MUX，由芯片内部驱动逻辑产生的旁路数据输入信号DI和由I / O接收的DQ信号数据总线缓冲接收电路。 I / O缓冲器的数据输入节点直接连接到新的多路复用器数据输入。提供附加的控制信号用于三个多路复用器数据输入的正交选择。

20. 发明授权

US5790892A Information handling system for modifying coherency response set to allow intervention of a read command so that the intervention is not allowed by the system memory 失效
标题翻译：用于修改一致性响应集的信息处理系统，以允许读取命令的干预，使得系统存储器不允许干预
公开(公告)号：US5790892A
公开(公告)日：1998-08-04
申请号：US536885
申请日：1995-09-29
申请人： John Michael Kaiser , Warren Edward Maule
发明人： John Michael Kaiser , Warren Edward Maule
IPC分类号： G06F12/08 , G06F13/16 , G06F13/00
CPC分类号： G06F12/0831 , G06F13/1673
摘要： An information handling system includes a number of processors, each connected to a processor bus, a memory controller connected to the processor bus which controls access to a system memory, a system controller, and one or more I/O controllers connected to the system bus where the system controller controls access to the system bus by all of the elements connected to the system bus, and the memory controller provides an efficient mechanism for handling data access to memory on read commands if a coherency response is modified. Combiner-prioritization logic in the memory controller includes logic in response to two additional inputs not shown in the prior art. The first logic responds to a read command and signals when a response window currently being combined is from a read command, and the second logic signals that the memory has an intervention buffer available to allow intervention.
摘要翻译：信息处理系统包括多个处理器，每个处理器连接到处理器总线，连接到处理器总线的存储器控制器，其控制对系统存储器的访问，系统控制器以及连接到系统总线的一个或多个I / O控制器其中系统控制器通过连接到系统总线的所有元件来控制对系统总线的访问，并且如果相关性响应被修改，则存储器控制器提供用于在读命令上处理对存储器的数据访问的有效机制。存储器控制器中的组合器优先级逻辑包括响应于现有技术中未示出的两个附加输入的逻辑。第一个逻辑响应一个读取命令，当当前正在组合的一个响应窗口来自一个读取命令时发出信号，第二个逻辑发出信号，指示该存储器有一个干预缓冲区可用于允许干预。

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