专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20060206557A1 Arithmetic logic unit circuit 有权
标题翻译：算术逻辑单元电路
公开(公告)号：US20060206557A1
公开(公告)日：2006-09-14
申请号：US11433333
申请日：2006-05-12
申请人： Anna Wing Wah Wong , Jennifer Wong , Bernard New , Alvin Ching , John Thendean , James Simkins , Vasisht Mantra Vadi , David Schultz
发明人： Anna Wing Wah Wong , Jennifer Wong , Bernard New , Alvin Ching , John Thendean , James Simkins , Vasisht Mantra Vadi , David Schultz
IPC分类号： G06F7/50
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.
摘要翻译：一种算术逻辑单元，包括耦合到第一加法器的第一多路复用器，由第一操作码寄存器控制的第一多路复用器; 第二多路复用器，从第一加法器接收输入并耦合到第二加法器; 以及用于控制第二多路复用器，第一加法器或第二加法器中的一个或多个的第二操作码寄存器。第一和第二操作码寄存器中的位的组合构成ALU以执行一个或多个算术运算或一个或多个逻辑运算或其任何组合。

12. 发明申请

US20050144212A1 Programmable logic device with cascading DSP slices 有权
标题翻译：具有级联DSP片的可编程逻辑器件
公开(公告)号：US20050144212A1
公开(公告)日：2005-06-30
申请号：US11019783
申请日：2004-12-21
申请人： James Simkins , Steven Young , Jennifer Wong , Bernard New , Alvin Ching
发明人： James Simkins , Steven Young , Jennifer Wong , Bernard New , Alvin Ching
IPC分类号： G06F15/00 , G06F15/78 , H03K19/177
CPC分类号： H03K19/17736 , G06F15/7867 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。每个DSP片包括多个操作数输入端口和片输出端口，所有这些端口都可编程地连接到通用路由和逻辑资源。操作数端口接收处理的操作数，切片输出端口传送处理结果。每个切片还包括连接到相应切片输出端口的反馈端口，以支持在该实施例中的累积功能，以及连接到上游切片的输出端口以支持级联的级联输入端口。

13. 发明申请

US20050144210A1 Programmable logic device with dynamic DSP architecture 有权
标题翻译：具有动态DSP架构的可编程逻辑器件
公开(公告)号：US20050144210A1
公开(公告)日：2005-06-30
申请号：US11019735
申请日：2004-12-21
申请人： James Simkins , Steven Young , Jennifer Wong , Bernard New , Alvin Ching
发明人： James Simkins , Steven Young , Jennifer Wong , Bernard New , Alvin Ching
IPC分类号： G06F15/00 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives mode control signals for dynamically altering the function and connectivity of related slices. Such alterations can occur with or without reconfiguring the PLD.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以级联的DSP片段，以创建不同大小和复杂度的DSP电路。每个片包括一个模式端口，它接收模式控制信号，用于动态地改变相关片段的功能和连通性。这种改变可以在或不配置PLD的情况下发生。

14. 发明申请

US20050144216A1 Arithmetic circuit with multiplexed addend inputs 有权
标题翻译：具有复用加法输入的算术电路
公开(公告)号：US20050144216A1
公开(公告)日：2005-06-30
申请号：US11019854
申请日：2004-12-21
申请人： James Simkins , Steven Young , Jennifer Wong , Bernard New , Alvin Ching
发明人： James Simkins , Steven Young , Jennifer Wong , Bernard New , Alvin Ching
IPC分类号： G06F7/509 , G06F15/00
CPC分类号： G06F7/509
摘要： Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.
摘要翻译：描述的是算术电路，逻辑上分为乘积发生器和加法器。逻辑上位于产品发生器和加法器之间的多路复用电路通过提供来自产品发生器的部分乘积到加法器的末端来支持常规功能。还可以控制复用电路以将多个外部添加的输入引导到加法器。附加加数输入可以包括从其他算术电路级联的输入和输出。

15. 发明申请

US20050144215A1 Applications of cascading DSP slices 有权
标题翻译：级联DSP片的应用
公开(公告)号：US20050144215A1
公开(公告)日：2005-06-30
申请号：US11019518
申请日：2004-12-21
申请人： James Simkins , Steven Young , Jennifer Wong , Bernard New , Alvin Ching
发明人： James Simkins , Steven Young , Jennifer Wong , Bernard New , Alvin Ching
IPC分类号： G06F15/00
CPC分类号： G06F7/5443
摘要： In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.
摘要翻译：在一个实施例中，公开了一种IC，其包括多个级联的数字信号处理片，其中每个片具有经由多路复用器耦合到加法器的乘法器，并且每个片与直接连接到相邻片; 以及用于通过例如opmode来配置多个数字信号处理片以执行一个或多个数学运算的装置。该IC允许实现一些基本的数学函数，例如加，减，乘和除。可以使用一个或多个DSP片段来实现许多其它应用，例如，累加，乘法累加（MACC），宽多路复用器，桶形移位器，计数器和折叠，抽取和内插FIR等等。

16. 发明申请

US20050144213A1 Mathematical circuit with dynamic rounding 有权
标题翻译：具有动态四舍五入的数学电路
公开(公告)号：US20050144213A1
公开(公告)日：2005-06-30
申请号：US11019853
申请日：2004-12-21
申请人： James Simkins , Steven Young , Jennifer Wong , Bernard New , Alvin Ching
发明人： James Simkins , Steven Young , Jennifer Wong , Bernard New , Alvin Ching
IPC分类号： G06F7/499 , G06F15/00
CPC分类号： G06F7/49963
摘要： Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M−1) and 2(M−1)−1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.
摘要翻译：描述了执行灵活舍入方案的数学电路。这些电路需要很少的额外资源，并且可以动态调整以改变舍入所涉及的位数。在一个实施例中，DSP电路存储从二进制数2（M-1）和2（M-1）-1组中选出的舍入常数，计算一个校正因子，并且舍入常数，校正因子和数据项，以获得舍入的数据项。

17. 发明申请

US20050144211A1 Programmable logic device with pipelined DSP slices 有权
标题翻译：可编程逻辑器件，带流水线DSP片
公开(公告)号：US20050144211A1
公开(公告)日：2005-06-30
申请号：US11019782
申请日：2004-12-21
申请人： James Simkins , Steven Young , Jennifer Wong , Bernard New , Alvin Ching
发明人： James Simkins , Steven Young , Jennifer Wong , Bernard New , Alvin Ching
IPC分类号： G06F15/00 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17732
摘要： Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.
摘要翻译：描述了可编程逻辑器件（PLD），其具有可以组合的DSP片段，以创建不同大小和复杂度的DSP电路。根据一些实施例的DSP片段包括可被配置为从零到两个时钟周期引入不同量的延迟的可编程操作数输入寄存器，例如以支持流水线化。在一个这样的实施例中，每个DSP片包括具有乘法器端口，被乘数端口和产品端口的部分乘积生成器。乘法器和被乘数端口通过相应的第一和第二操作数输入寄存器连接到操作数输入端口，每个第一和第二操作数输入寄存器能够从零延迟到两个延迟的时钟周期。在另一个实施例中，至少一个操作数输入寄存器的输出可以连接到下游DSP片的操作数输入寄存器的输入，使得操作数可以在一个或多个片之间传送。

18. 发明申请

US20070035328A1 Configurable logic element with expander structures 有权
公开(公告)号：US20070035328A1
公开(公告)日：2007-02-15
申请号：US11585534
申请日：2006-10-24
申请人： Bernard New , Ralph Wittig , Sundararajarao Mohan
发明人： Bernard New , Ralph Wittig , Sundararajarao Mohan
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , H03K19/1731 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

19. 发明申请

US20050039155A1 FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same 有权
公开(公告)号：US20050039155A1
公开(公告)日：2005-02-17
申请号：US10941248
申请日：2004-09-15
申请人： Bernard New
发明人： Bernard New
IPC分类号： H03K19/177 , G06F17/50 , G06F9/45
CPC分类号： H03K19/17736 , H03K19/17784 , H03K19/17792
摘要： An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments, the transistors of the first and second subsets have different threshold voltages. Transistors in the first subset, being optimized for speed, have a lower threshold voltage than transistors in the second subset, which are optimized for low power consumption. The difference in threshold voltages can be accomplished by using different doping levels, wells biased to different voltage levels, or using other well-known means. In some embodiments, the first subset of the interconnect resources includes buffers coupled to a higher voltage level than the second subset. In some embodiments, the first subset includes buffers manufactured using larger transistors than those in the second subset.

20. 发明申请

US20050021749A1 Method and apparatus for communication within a programmable logic device using serial transceivers 有权
标题翻译：使用串行收发器的可编程逻辑器件内的通信方法和装置
公开(公告)号：US20050021749A1
公开(公告)日：2005-01-27
申请号：US10420418
申请日：2003-04-21
申请人： Adam Donlin , Bernard New
发明人： Adam Donlin , Bernard New
IPC分类号： H03K19/177 , G06F15/173
CPC分类号： H03K19/17736
摘要： Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module. The first module and the second module each include a transceiver coupled to a serial/parallel interface, with each transceiver configured with at least one signal conductor for serial communication between the first module and the second module. The first module and the second module are configured to communicate with one another asynchronously. Each transceiver is configured to communicate with its respective serial/parallel interface in a synchronous time domain.
摘要翻译：描述了使用串行收发器的可编程逻辑器件内的通信方法和装置。在一个示例中，集成电路包括第一模块和第二模块。第一模块和第二模块各自包括耦合到串行/并行接口的收发器，每个收发器配置有用于第一模块和第二模块之间的串行通信的至少一个信号导体。第一模块和第二模块被配置为异步地彼此通信。每个收发器被配置为在同步时域中与其各自的串行/并行接口进行通信。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式