专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20080237751A1 CMOS Structure and method of manufacturing same 审中-公开
标题翻译： CMOS结构及其制造方法
公开(公告)号：US20080237751A1
公开(公告)日：2008-10-02
申请号：US11731163
申请日：2007-03-30
申请人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Willy Rachmady
发明人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Willy Rachmady
IPC分类号： H01L21/8238
CPC分类号： H01L21/82385 , H01L29/785
摘要： A CMOS structure includes a substrate (110, 310), an electrically insulating layer (120, 320) over the substrate, NMOS (130, 330) and PMOS (140, 340) semiconducting structures over the electrically insulating layer, and a dielectric layer (150, 350) having first (151, 351) and second (152, 352) portions over, respectively, the NMOS and PMOS semiconducting structures. The NMOS and PMOS semiconducting structures have, respectively, a first height (135, 335) and a second height (145, 345). The CMOS structure further includes a first electrically conducting layer (160, 360) over the first portion of the dielectric layer, a second electrically conducting layer (170, 370) over the second portion of the dielectric layer and thicker than the first electrically conducting layer, a first polysilicon layer (180, 780) over the first electrically conducting layer, and a second polysilicon layer (190, 790) over the second electrically conducting layer and thinner than the first polysilicon layer.
摘要翻译： CMOS结构包括衬底（110,310），衬底上的电绝缘层（120,320），电绝缘层上的NMOS（130,330）和PMOS（140,340）半导体结构，以及介电层（150,350）分别在NMOS和PMOS半导体结构之上具有第一（151,351）和第二（152,352）部分。 NMOS和PMOS半导体结构分别具有第一高度（135,335）和第二高度（145,345）。 CMOS结构还包括位于电介质层的第一部分上的第一导电层（160,360），在介电层的第二部分上方的第二导电层（170,370），并且比第一导电层，在所述第一导电层上方的第一多晶硅层（180,780）以及所述第二导电层上的第二多晶硅层（190,790）并且比所述第一多晶硅层更薄。

12. 发明申请

US20080003755A1 Sacrificial oxide layer which enables spacer over-etch in tri-gate architectures 审中-公开
标题翻译：牺牲氧化物层，其在三栅结构中实现间隔体过蚀刻
公开(公告)号：US20080003755A1
公开(公告)日：2008-01-03
申请号：US11479713
申请日：2006-06-30
申请人： Uday Shah , Willy Rachmady , Jack T. Kavalieros , Brian S. Doyle
发明人： Uday Shah , Willy Rachmady , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/66795 , H01L29/7851
摘要： Embodiments of methods and apparatus for a sacrificial oxide layer which enables spacer over-etch in multi-gate architectures are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述了能够在多门体系结构中实现间隔物过蚀刻的牺牲氧化物层的方法和装置的实施例。可以描述和要求保护其他实施例。

13. 发明授权

US08193567B2 Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby 有权
标题翻译：用于将体积衬底上的平面和非平面CMOS晶体管和由此制成的制品集成的工艺
公开(公告)号：US08193567B2
公开(公告)日：2012-06-05
申请号：US12333248
申请日：2008-12-11
申请人： Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
发明人： Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L29/76
CPC分类号： H01L21/823828 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/1037 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
摘要翻译：一种能够将平面和非平面晶体管集成到体半导体衬底上的工艺，其中所有晶体管的沟道可在连续的宽度范围内定义。

14. 发明申请

US20110284965A1 REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES 审中-公开
标题翻译：使用间隔加工技术降低多门装置的外部电阻
公开(公告)号：US20110284965A1
公开(公告)日：2011-11-24
申请号：US13204987
申请日：2011-08-08
申请人： Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
发明人： Ravi Pillarisetty , Uday Shah , Brian S. Doyle , Jack T. Kavalieros
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/785
摘要： Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more to multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.
摘要翻译：通常描述使用间隔物处理技术降低多栅极器件的外部电阻。在一个示例中，一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上，一个或多个多栅极鳍片包括栅极区域，源极区域和漏极区域，栅极区域设置在源极和漏极区域，图案化牺牲栅极电极，使得牺牲栅电极材料耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到一个或多个多栅极鳍片的源极和漏极区域，形成电介质将一个或多个多栅极翅片的源极和漏极区域耦合到所述一个或多个多栅极散热片的栅极区域;将所述牺牲栅极电极从所述一个或多个至多个栅极鳍片的栅极区域移除;将间隔栅极电介质沉积到所述一个或多个栅极栅极栅极区域; 更多的多栅极鳍片，其中基本上没有间隔栅极电介质沉积到一个或多个多栅极鳍片的源极和漏极区域，源极和漏极区域被电介质保护膜和蚀刻间隔栅极电介质以从栅极区域区域完全去除间隔栅极电介质，以与最终栅极电极耦合，除了与保持耦合的最终栅电极耦合的间隔栅极电介质的剩余预定厚度之外与电介质膜。

15. 发明授权

US07700470B2 Selective anisotropic wet etching of workfunction metal for semiconductor devices 失效
标题翻译：半导体器件功能金属的选择性各向异性湿蚀刻
公开(公告)号：US07700470B2
公开(公告)日：2010-04-20
申请号：US11525765
申请日：2006-09-22
申请人： Willy Rachmady , Uday Shah , Jack T. Kavalieros , Brian S. Doyle
发明人： Willy Rachmady , Uday Shah , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842 , H01L21/823821 , H01L27/092 , H01L27/0924 , H01L29/66795 , H01L29/785
摘要： Embodiments of an apparatus and methods for providing a workfunction metal gate electrode on a substrate with doped metal oxide semiconductor structures are generally described herein. Other embodiments may be described and claimed.
摘要翻译：在此通常描述用于在具有掺杂金属氧化物半导体结构的衬底上提供功函数金属栅电极的装置和方法的实施例。可以描述和要求保护其他实施例。

16. 发明授权

US07479421B2 Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby 有权
标题翻译：用于将体积衬底上的平面和非平面CMOS晶体管和由此制成的制品集成的工艺
公开(公告)号：US07479421B2
公开(公告)日：2009-01-20
申请号：US11238444
申请日：2005-09-28
申请人： Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
发明人： Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L21/8234
CPC分类号： H01L21/823828 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/1037 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
摘要翻译：一种能够将平面和非平面晶体管集成到体半导体衬底上的工艺，其中所有晶体管的沟道可在连续的宽度范围内定义。

17. 发明授权

US07435683B2 Apparatus and method for selectively recessing spacers on multi-gate devices 有权
标题翻译：用于在多栅极器件上选择性地凹入间隔物的装置和方法
公开(公告)号：US07435683B2
公开(公告)日：2008-10-14
申请号：US11521624
申请日：2006-09-15
申请人： Jack T. Kavalieros , Uday Shah , Willy Rachmady , Brian S. Doyle
发明人： Jack T. Kavalieros , Uday Shah , Willy Rachmady , Brian S. Doyle
IPC分类号： H01L21/461
CPC分类号： H01L29/4983 , H01L29/66628 , H01L29/66795 , H01L29/785 , Y10S257/90
摘要： Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述用于在多栅极晶体管的一部分上制造间隔物而不在多栅极晶体管的另一部分上形成间隔物的方法的实施例。可以描述和要求保护其他实施例。

18. 发明申请

US20080157207A1 TRI-GATE DEVICE WITH CONFORMAL PVD WORKFUNCTION METAL ON ITS THREE-DIMENSIONAL BODY AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：具有合适PVD功能金属的三栅极器件及其三维体及其制造方法
公开(公告)号：US20080157207A1
公开(公告)日：2008-07-03
申请号：US12044225
申请日：2008-03-07
申请人： Willy Rachmady , Brian S. Doyle , Jack T. Kavalieros , Uday Shah
发明人： Willy Rachmady , Brian S. Doyle , Jack T. Kavalieros , Uday Shah
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： A method of fabricating a tri-gate semiconductor device comprising a semiconductor body having an upper surface and side surfaces and a metal gate that has an approximately equal thickness on the upper and side surfaces. Embodiments of a tri-gate device with conformal physical vapor deposition workfunction metal on its three-dimensional body are described herein. Other embodiments may be described and claimed.
摘要翻译：一种制造三栅极半导体器件的方法，包括具有上表面和侧表面的半导体本体和在上表面和侧表面上具有大致相同厚度的金属栅极。本文描述了具有保形物理气相沉积功能金属的三栅极器件在其三维体上的实施例。可以描述和要求保护其他实施例。

19. 发明申请

US20080121998A1 Apparatus and method for selectively recessing spacers on multi-gate devices 有权
公开(公告)号：US20080121998A1
公开(公告)日：2008-05-29
申请号：US11521624
申请日：2006-09-15
申请人： Jack T. Kavalieros , Uday Shah , Willy Rachmady , Brian S. Doyle
发明人： Jack T. Kavalieros , Uday Shah , Willy Rachmady , Brian S. Doyle
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L29/66628 , H01L29/66795 , H01L29/785 , Y10S257/90
摘要： Embodiments of an apparatus and methods for fabricating a spacer on one part of a multi-gate transistor without forming a spacer on another part of the multi-gate transistor are generally described herein. Other embodiments may be described and claimed.

20. 发明申请

US20090166742A1 REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE BY INCORPORATION OF A PARTIAL METALLIC FIN 有权
标题翻译：通过加入部分金属粉末来降低多门装置的外部电阻
公开(公告)号：US20090166742A1
公开(公告)日：2009-07-02
申请号：US11964623
申请日：2007-12-26
申请人： Ravi Pillarisetty , Uday Shah , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
发明人： Ravi Pillarisetty , Uday Shah , Titash Rakshit , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L29/94 , H01L21/8234
CPC分类号： H01L29/785 , H01L29/66795
摘要： Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin is generally described. In one example, an apparatus includes a semiconductor substrate and one or more fins of a multi-gate transistor device coupled with the semiconductor substrate, the one or more fins having a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions where the gate region of the one or more fins includes a semiconductor material and where the source and drain regions of the one or more fins include a metal portion and a semiconductor portion, the metal portion and the semiconductor portion being coupled together.
摘要翻译：通常描述通过结合部分金属翅片来降低多栅极器件的外部电阻。在一个示例中，设备包括半导体衬底和与半导体衬底耦合的多栅极晶体管器件的一个或多个鳍片，该一个或多个鳍片具有栅极区域，源极区域和漏极区域，栅极区域设置在源极和漏极区域之间，其中一个或多个鳍片的栅极区域包括半导体材料，并且其中一个或多个鳍片的源极和漏极区域包括金属部分和半导体部分，金属部分和半导体部分联接在一起。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式