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11. 发明授权

US5371031A Method of making EEPROM array with buried N+ windows and with separate erasing and programming regions 失效
标题翻译：制造具有埋入式N +窗口并具有单独擦除和编程区域的EEPROM阵列的方法
公开(公告)号：US5371031A
公开(公告)日：1994-12-06
申请号：US89206
申请日：1993-07-09
申请人： Manzur Gill , Inn K. Lee
发明人： Manzur Gill , Inn K. Lee
IPC分类号： H01L21/8247 , H01L21/70
CPC分类号： H01L27/11521
摘要： An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). The source line (17) consists of alternating buried N+ windows (17a) and source regions (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). The memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) through the tunnel window (13a) to the source-line (17). The program and erase regions of the cells are physically separate from each other, and the characteristics, including the oxides, of each of those regions may be made optimum independently from each other.
摘要翻译：在半导体衬底（22）的表面上成对地形成电可擦除的电可编程的只读存储单元阵列。每个存储单元包括源极区域（11）和漏极区域（12），其间具有相应的沟道区域。福勒 - 诺德海姆隧道窗口（13a）位于连接到源（11）的源极线（17）上。源极线（17）由交替的掩埋N +窗口（17a）和源极区域（11）组成。浮动门（13）包括隧道窗部分。控制栅极（14）设置在浮置栅极（13）上，由中间层间电介质（27）绝缘。浮动栅极（13）和控制栅极（14）包括通道部分（Ch）。通道部分（Ch）用作源（11）和漏极（12）区域的自对准注入掩模，使得沟道结边缘与通道部分（Ch）的相应边缘对齐。存储单元通过从通道的热载流子注入到浮动栅极（13）进行编程，并由Fowler-Nordheim从浮动栅极（13）通过隧道窗口（13a）到源极线（17）的隧道擦除，。单元的程序和擦除区域在物理上彼此分离，并且这些区域中的每一个的特性，包括氧化物可以彼此独立地最优化。

12. 发明授权

US5218568A Electrically-erasable, electrically-programmable read-only memory cell, an array of such cells and methods for making and using the same 失效
标题翻译：电可擦除的电可编程只读存储器单元，这样的单元阵列以及制造和使用它们的方法
公开(公告)号：US5218568A
公开(公告)日：1993-06-08
申请号：US809462
申请日：1991-12-17
申请人： Sung-Wei Lin , Manzur Gill , Inn K. Lee
发明人： Sung-Wei Lin , Manzur Gill , Inn K. Lee
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11524
摘要： An electrically-erasable, electrically-programmable read-only memory cell 10 is formed at a face of a layer of semiconductor 30 of a first conductivity type. A first source/drain region 16 and a second source/drain region 20 are formed in the face of layer of semiconductor 30 of a second conductivity type opposite the first conductivity type and spaced by a first channel area 50. A third source/drain region 18 is formed in the face of semiconductor layer 30 of the second conductivity type spaced from second source/drain region 20 by a second channel area 52. A thick insulator region 44 is formed adjacent at least a portion of second source/drain region 20 and includes a lateral margin of sloped thickness overlying a corresponding lateral margin of second source/drain region 20. The corresponding lateral margin of second source/drain region 20 has a graded dopant concentration directly proportionate with the sloped thickness of the overlying lateral margin of thick insulator region 44. A differentially grown insulator region 54 overlies second source/drain region 20 and includes a lateral margin of sloped thickness. A thin insulator tunneling window 62 overlies an area 60 of second source/drain region 20, tunneling window 62 formed between and spacing the lateral margin of the thick insulator region 44 and the lateral margin of differentially grown insulator region 54. A floating gate conductor 26 is disposed adjacent tunneling window 62 and insulatively adjacent second channel area 52. A control gate conductor 28 is disposed insulatively adjacent floating gate conductor 28. A gate conductor 24 is disposed insulatively adjacent first channel area 50.
摘要翻译：电可擦除的电可编程只读存储单元10形成在第一导电类型的半导体层30的表面。第一源极/漏极区域16和第二源极/漏极区域20形成在与第一导电类型相反并且由第一沟道区域50间隔开的第二导电类型的半导体层30的表面中。第三源极/漏极区域 18形成在第二导电类型的半导体层30的表面上，第二导电类型的第二导电类型与第二源极/漏极区域20间隔开第二沟道区域52.邻近第二源极/漏极区域20的至少一部分形成厚的绝缘体区域44，包括覆盖第二源极/漏极区域20的相应横向边缘的倾斜厚度的横向边缘。第二源极/漏极区域20的对应横向边缘具有与厚度绝缘体的上覆侧边缘的倾斜厚度成正比的渐变掺杂剂浓度差分生长的绝缘体区域54覆盖第二源极/漏极区域20并且包括倾斜厚度的侧向边缘。薄的绝缘体隧道窗口62覆盖在第二源极/漏极区域20的区域60之间，形成在厚绝缘体区域44的侧边缘之间并且间隔着厚的绝缘体区域44的侧边缘和差分生长的绝缘体区域54的横向边缘之间的隧道窗口62.浮动栅极导体26 被布置在相邻的隧道窗口62和绝对相邻的第二通道区域52处。控制栅极导体28被隔离地邻近浮置栅极导体28设置。栅极导体24与第一沟道区域50绝缘地邻近设置。

13. 发明授权

US5155055A Method of making an electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel 失效
标题翻译：制造具有自对准隧道的电可擦除，电可编程只读存储器单元的方法
公开(公告)号：US5155055A
公开(公告)日：1992-10-13
申请号：US685358
申请日：1991-04-15
申请人： Manzur Gill , Sung-Wei Lin , C. Rinn Cleavelin , David J. McElroy
发明人： Manzur Gill , Sung-Wei Lin , C. Rinn Cleavelin , David J. McElroy
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883
摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.
摘要翻译：使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。

14. 发明授权

US5057446A Method of making an EEPROM with improved capacitive coupling between control gate and floating gate 失效
标题翻译：制造具有改善的控制栅极和浮动栅极之间的电容耦合的EEPROM的方法
公开(公告)号：US5057446A
公开(公告)日：1991-10-15
申请号：US563369
申请日：1990-08-06
申请人： Manzur Gill , David J. McElroy
发明人： Manzur Gill , David J. McElroy
IPC分类号： H01L21/28 , H01L21/8247 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/7883
摘要： According to the invention, an integrated circuit with improved capacitive coupling is provided, and includes a first conductor (20), a second conductor (16), and a third conductor (22). The second conductor (22) and third conductor (16) are disposed adjacent each other, separated by an insulator region (60). The first conductor (20) contacts the third conductor (16) and extends across a portion of the third conductor (22). The first and third conductors are separated by an insulator region (54). A voltage applied to first conductor (20) and second conductor (16) is capacitively coupled to third conductor (22).
摘要翻译：根据本发明，提供了具有改进的电容耦合的集成电路，并且包括第一导体（20），第二导体（16）和第三导体（22）。第二导体（22）和第三导体（16）彼此相邻设置，由绝缘体区域（60）分开。第一导体（20）接触第三导体（16）并延伸穿过第三导体（22）的一部分。第一和第三导体被绝缘体区域（54）隔开。施加到第一导体（20）和第二导体（16）的电压电容耦合到第三导体（22）。

15. 发明授权

US5051796A Cross-point contact-free array with a high-density floating-gate structure 失效
标题翻译：具有高密度浮栅结构的交叉点无接触阵列
公开(公告)号：US5051796A
公开(公告)日：1991-09-24
申请号：US403065
申请日：1989-09-01
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L27/115
CPC分类号： H01L27/115
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicated NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines having a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Bitline isolation is by P/N junction or by oxide-filled trench, permitting relatively small spacing between transistors. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：无接触式浮栅非易失性存储单元阵列和具有硅胶NSAG位线和掩埋在相对厚的氧化硅之下的源/漏区的工艺。位线具有相对较小的电阻，消除了对具有许多位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。位线隔离是通过P / N结或通过氧化物填充沟槽，允许晶体管之间的间隔相对较小。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过在控制栅极和浮置栅极之间使用具有相对较高介电常数的绝缘体来提高编程和擦除电压到浮栅的耦合。所得到的结构是可编程存储器单元的密集交叉点阵列。

16. 发明授权

US5045491A Method of making a nonvolatile memory array having cells with separate program and erase regions 失效
标题翻译：制造具有单独的程序和擦除区域的单元的非易失性存储器阵列的方法
公开(公告)号：US5045491A
公开(公告)日：1991-09-03
申请号：US589342
申请日：1990-09-28
申请人： Manzur Gill , Theodore D. Lindgren
发明人： Manzur Gill , Theodore D. Lindgren
IPC分类号： H01L21/336 , H01L21/8247 , H01L29/788
CPC分类号： H01L27/11521 , H01L29/66825 , H01L29/7883 , Y10S438/981
摘要： A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first and second sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor permits programming of the cells through the first tunnelling window only and erasing of the cells through the second tunnelling window only, or vice versa.
摘要翻译：具有用于编程和擦除的分离区域的非易失性存储单元。电池在半导体本体的表面上以阵列形成，每个电池包括作为源 - 列线的一部分的源，并且包括作为漏 - 列线的一部分的漏极。每个单元在源极和漏极之间具有第一和第二子通道。每个电池单元的第一子通道的电导率由场板控制，该场板是位于第一子通道上并与第一子通道绝缘的场板 - 列 - 列线的一部分。每个第二子通道的电导率由形成在第二子通道上并与第二子通道绝缘的浮动栅极控制。每个浮动栅极具有位于相邻源极列线上方的第一隧道窗口，并且具有位于相邻排列 - 列线上方的第二隧道窗口。包括控制栅极的行线位于单元的浮动栅极的上方并与之隔绝，用于读取，编程和擦除单元。场板导体仅允许通过第一隧道窗口对单元进行编程，并且仅通过第二隧道窗口擦除单元，反之亦然。

17. 发明授权

US5025494A Cross-point contact-free floating-gate memory array with silicided buried bitlines 失效
标题翻译：具有硅化掩埋位线的交叉点无接触浮栅存储器阵列
公开(公告)号：US5025494A
公开(公告)日：1991-06-18
申请号：US269838
申请日：1988-11-10
申请人： Manzur Gill , David J. McElroy
发明人： Manzur Gill , David J. McElroy
IPC分类号： H01L27/115
CPC分类号： H01L27/115
摘要： A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.
摘要翻译：一个无接触的浮栅非易失性存储单元阵列和具有硅化NSAG位线的工艺，以及埋在相对厚的氧化硅之下的源/漏区。位线具有相对较小的电阻，消除了对具有大量位线触点的并行金属导体的需要。阵列具有相对小的位线电容，并且可以构造成具有相对较小的尺寸。字线之间和位线之间的隔离是通过厚场氧化物。字线可以由具有低电阻率的硅化多晶或其它材料形成。通过将栅极扩展到厚场氧化物上并且可能通过在控制栅极和浮置栅极之间使用具有相对高的介电常数的绝缘体来改善编程和擦除电压到浮栅的耦合。所得到的结构是可编程存储器单元的密集交叉点阵列。

18. 发明授权

US5017515A Process for minimizing lateral distance between elements in an integrated circuit by using sidewall spacers 失效
标题翻译：通过使用侧壁间隔来最小化集成电路中的元件之间的横向距离的方法
公开(公告)号：US5017515A
公开(公告)日：1991-05-21
申请号：US415807
申请日：1989-10-02
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L21/027 , H01L21/033 , H01L21/316 , H01L21/762 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11519 , H01L21/02238 , H01L21/02255 , H01L21/0271 , H01L21/033 , H01L21/31662 , H01L21/76221 , H01L27/115 , H01L27/11521
摘要： The process of this invention includes forming and patterning a first layer of photoresist to form first lines of photoresist having substantially minimum lithographic widths, forming first elements between the first lines of photoresist, removing the photoresist, forming a sidewall member on each side edge of the first elements, forming a second layer over the structure, and etching to electrically insulate the first elements and the second elements at the sidewalls. Alternatively, the structure is coated with another layer of photoresist after formation of sidewall member on each side of the first elements. The layer of photoresist is patterned to form second photoresist lines that cover alternating sidewall members. The exposed sidewall members are removed. Strips are formed between the second photoresist lines. After removal of the second photoresist lines, the structure is etched as before. However, in this embodiment, lateral extensions of the first elements are formed. The combined elements are separated by the remaining sidewall members.
摘要翻译：本发明的方法包括形成和图案化第一层光致抗蚀剂以形成具有基本最小平版印刷宽度的第一行光致抗蚀剂，在第一光致抗蚀剂线之间形成第一元件，去除光致抗蚀剂，在该光刻胶的每个侧边缘上形成侧壁部件第一元件，在结构上形成第二层，以及蚀刻以使第一元件和第二元件在侧壁处电绝缘。或者，在第一元件的每一侧上形成侧壁构件之后，该结构被另一层光致抗蚀剂涂覆。图案化光致抗蚀剂层以形成覆盖交替侧壁构件的第二光致抗蚀剂线。暴露的侧壁件被去除。在第二光致抗蚀剂线之间形成条纹。在除去第二光致抗蚀剂线之后，如前所述蚀刻结构。然而，在本实施例中，形成第一元件的横向延伸。组合的元件由剩余的侧壁构件分开。

19. 发明授权

US5008721A Electrically-erasable, electrically-programmable read-only memory cell with self-aligned tunnel 失效
标题翻译：具有自对准隧道的电可擦除电可编程只读存储单元
公开(公告)号：US5008721A
公开(公告)日：1991-04-16
申请号：US494042
申请日：1990-03-15
申请人： Manzur Gill , Sung-Wei Lin , C. Rinn Cleavelin , David J. McElroy
发明人： Manzur Gill , Sung-Wei Lin , C. Rinn Cleavelin , David J. McElroy
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/11517 , H01L29/7883 , Y10S257/903
摘要： An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using an enhancement transistor merged with a floating-gate transistor, where the floating-gate transistor has a small self-aligned tunnel window positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide, which allows a favorable ratio of control gate to floating gate capacitance. Programming and erasing are provided by the tunnel window area on the outside of the source (spaced from the channel). The tunnel window has a thinner dielectric than the remainder of the floating gate to allow Fowler-Nordheim tunneling.
摘要翻译：使用与浮栅晶体管合并的增强型晶体管构造电可擦除的电可编程ROM或EEPROM，其中浮栅晶体管具有位于源极的相对侧上的小的自对准隧道窗口通道和漏极，无接触电池布局，增强了制造的便利性和减小电池尺寸。在该单元中，位线和源极/漏极区域被埋在相对较厚的氧化硅之下，这允许控制栅极与浮动栅极电容的有利比例。编程和擦除由源外部的隧道窗口区域（与通道间隔开）提供。隧道窗口具有比浮动门的其余部分更薄的电介质，以允许Fowler-Nordheim隧道。

20. 发明授权

US4994403A Method of making an electrically programmable, electrically erasable memory array cell 失效
标题翻译：制造电可编程，电可擦除存储器阵列单元的方法
公开(公告)号：US4994403A
公开(公告)日：1991-02-19
申请号：US457990
申请日：1989-12-28
申请人： Manzur Gill
发明人： Manzur Gill
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7885
摘要： A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective drain regions (30a, 30b), a shared source region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) which may be programmed by hot electron injection and erased by Fowler-Nordheim electron tunneling through respective tunneling oxide windows (40a, 40b) overlying a portion of source region (28) adjacent respective channels (38a, 38b). A wordline or control gate conductor (62) is insulatively disposed adjacent the floating gates (46a, 46b) to program or erase.
摘要翻译：在半导体层（10）的表面上形成一对电可擦除的电可编程存储器单元，并且包括各自的漏极区域（30a，30b），共享源极区域（28）和相应的沟道区域（38a，38b）。每个单元具有浮动栅极导体（46a，46b），其可以通过热电子注入来编程，并且通过Fowler-Nordheim电子隧穿通过覆盖邻近相应通道的源极区域（28）的一部分的相应隧道氧化物窗口（40a，40b）（38a，38b）。与浮动栅极（46a，46b）相邻地绝缘地布置字线或控制栅极导体（62）以进行编程或擦除。

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