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11. 发明申请

US20120262209A1 Multi-Phase Clock Generator and Data Transmission Lines 有权
标题翻译：多相时钟发生器和数据传输线
公开(公告)号：US20120262209A1
公开(公告)日：2012-10-18
申请号：US13089160
申请日：2011-04-18
申请人： Yung-Chow Peng , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Yung-Chow Peng , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03K5/15066 , H03K5/133 , H03K2005/00058 , H03L7/06
摘要： An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.
摘要翻译：实施例是集成电路。集成电路包括时钟发生器和数据传输线。时钟发生器产生时钟信号。至少一些时钟信号具有与输入到时钟发生器的输入时钟信号的相位差，并且至少一些时钟信号相对于至少另一个时钟信号具有不同的相位差。至少部分地通过至少一个时钟信号来触发每个数据传输线。

12. 发明授权

US06593775B2 Insulatior for a multi-power system 失效
公开(公告)号：US06593775B2
公开(公告)日：2003-07-15
申请号：US09761930
申请日：2001-01-17
申请人： Kou-Hwa Yu , Jui-Chiang Wang , Yung-Chow Peng
发明人： Kou-Hwa Yu , Jui-Chiang Wang , Yung-Chow Peng
IPC分类号： H03K19185
CPC分类号： G06F1/32 , G06F1/26
摘要： This invention relates to an insulator for a multi-power system, which is used to resolve the current leakage which comes from each power supplied to the corresponding devices which are not being correctly operated. The isolating device includes: a first power supply for providing an operating power to the isolating device; a level detector for detecting the voltage level of the operating power; a signal isolation controller for changing the output level of the circuit supplied by the operating power based on the operating power detected; and a second power for supplying a real-time power to circuit for power saving operation based on the changed output level.

13. 发明授权

US06473282B1 Latch-up protection circuit for integrated circuits biased with multiple power supplies and its method 失效
标题翻译：用于多电源偏置的集成电路的锁存保护电路及其方法
公开(公告)号：US06473282B1
公开(公告)日：2002-10-29
申请号：US09547186
申请日：2000-04-11
申请人： Shi-Tron Lin , Ta-Lee Yu , Yung-Chow Peng
发明人： Shi-Tron Lin , Ta-Lee Yu , Yung-Chow Peng
IPC分类号： H02H320
CPC分类号： H01L27/0251
摘要： A latch-up protection circuit for an integrated circuit powered through a first power rail and a second power rail is disclosed, the integrated circuit having at least one semiconductor bulk of a conductivity type. The latch-up protection circuit comprises a control circuit and a switch circuit. The control circuit is connected to the first power rail and the second power rail for detecting a relative voltage therebetween and generating a first control signal and a second control signal. The switch circuit connected to the first power rail and the control circuit. When the relative voltage is greater than a first predetermined value, the switch circuit in response to the first control signal electrically connects the first power rail with the at least one semiconductor bulk. When the relative voltage is smaller than the first predetermined value, the switch in response to the first control signal electrically disconnects the first power rail from the at least one semiconductor bulk.
摘要翻译：公开了一种用于通过第一电力轨道和第二电力轨道供电的集成电路的闩锁保护电路，该集成电路具有至少一个导电类型的半导体本体。闩锁保护电路包括控制电路和开关电路。控制电路连接到第一电源轨和第二电源轨，用于检测它们之间的相对电压，并产生第一控制信号和第二控制信号。开关电路连接到第一电源轨和控制电路。当相对电压大于第一预定值时，响应于第一控制信号的开关电路将第一电源轨与至少一个半导体块电连接。当相对电压小于第一预定值时，响应于第一控制信号的开关将第一电力轨与至少一个半导体块电气断开。

14. 发明授权

US08762897B2 Semiconductor device design system and method of using the same 有权
标题翻译：半导体器件设计系统及其使用方法
公开(公告)号：US08762897B2
公开(公告)日：2014-06-24
申请号：US13475853
申请日：2012-05-18
申请人： Chih-Hsien Chang , Yung-Chow Peng , Fu-Lung Hsueh
发明人： Chih-Hsien Chang , Yung-Chow Peng , Fu-Lung Hsueh
IPC分类号： G06F17/50 , G03F1/00 , G21K5/00 , G06F19/00
CPC分类号： G06F17/5081 , G03F1/00 , G06F17/5009 , G06F17/5045 , G06F17/5068 , G06F19/00 , G06F2217/12 , G21K5/00
摘要： A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.
摘要翻译：电路设计系统包括被配置为产生电路的示意图信息和预着色信息的示意性设计工具。电路设计系统还包括被配置为在非暂时计算机可读介质上存储原理图信息和预着色信息的网表文件，以及被配置为从网表文件中提取预着色信息的提取工具。包括在电路设计系统中的布局设计工具被配置为基于原理图信息和预着色信息设计至少一个掩模。电路设计系统还包括布局与示意性比较工具，其被配置为将至少一个掩模与示意图信息和预着色信息进行比较。

15. 发明授权

US08629795B2 Micro-electro-mechanical systems (MEMS), systems, and operating methods thereof 有权
标题翻译：微电子机械系统（MEMS），系统及其操作方法
公开(公告)号：US08629795B2
公开(公告)日：2014-01-14
申请号：US12856993
申请日：2010-08-16
申请人： Yung-Chow Peng , Wen-Hung Huang , Yu-Wei Lin
发明人： Yung-Chow Peng , Wen-Hung Huang , Yu-Wei Lin
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , B81B7/008 , H03M1/0626 , H03M1/12 , H03M3/30
摘要： A micro-electro-mechanical system (MEMS) includes a micro-mechanical structure that is capable of generating a first electrical signal. An analog-to-digital converter (ADC) is coupled with the micro-mechanical structure. The MEMS is free from including any amplifier between the micro-mechanical structure and the ADC.
摘要翻译：微电子机械系统（MEMS）包括能够产生第一电信号的微机械结构。模数转换器（ADC）与微机械结构耦合。 MEMS不包括微机械结构和ADC之间的任何放大器。

16. 发明申请

US20130185688A1 OVER STRESS VERIFY DESIGN RULE CHECK 有权
标题翻译：超过应变验证设计规则检查
公开(公告)号：US20130185688A1
公开(公告)日：2013-07-18
申请号：US13350894
申请日：2012-01-16
申请人： Chen-Ting Ko , Chih-Hsien Chang , Yung-Chow Peng
发明人： Chen-Ting Ko , Chih-Hsien Chang , Yung-Chow Peng
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured.
摘要翻译：本公开的一些方面提供了电子设计自动化（EDA）技术，其在设计期间检查诸如晶体管或其他半导体器件的各个块是否连接到其正确的电源域。以这种方式，所公开的EDA技术可以限制或防止在制造时应用于块的过应力条件并有助于提高集成电路的可靠性。

17. 发明授权

US08476971B2 Buffer operational amplifier with self-offset compensator and embedded segmented DAC for improved linearity LCD driver 有权
标题翻译：具有自偏置补偿器和嵌入式分段DAC的缓冲运算放大器，用于改进线性LCD驱动器
公开(公告)号：US08476971B2
公开(公告)日：2013-07-02
申请号：US12889492
申请日：2010-09-24
申请人： Yung-Chow Peng , Wen-Shen Chou , Ching-Ho Chang , Wan-Te Chen
发明人： Yung-Chow Peng , Wen-Shen Chou , Ching-Ho Chang , Wan-Te Chen
IPC分类号： G06G7/12
CPC分类号： G09G3/3688 , G09G2310/027
摘要： A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range.
摘要翻译：驱动器利用运算放大器的端子的选择性偏置来减小运算放大器输出中的偏移。每个运算放大器输入包括包括NMOS晶体管和PMOS晶体管的差分输入对晶体管。在输入电压范围的低端和高端，这些晶体管选择性地和单独地耦合到标准输入或偏置为导通，以便补偿偏移补偿。晶体管以常规方式偏置，用于在电压范围的低端和高端之间的输入电压。

18. 发明申请

US20120235208A1 Semiconductor Mismatch Reduction 有权
标题翻译：半导体失配减少
公开(公告)号：US20120235208A1
公开(公告)日：2012-09-20
申请号：US13048411
申请日：2011-03-15
申请人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
发明人： Chung-Hui Chen , Ruey-Bin Sheen , Yung-Chow Peng , Po-Zeng Kang , Chung-Peng Hsieh
IPC分类号： H01L29/12 , H01L21/66
CPC分类号： H01L27/0207
摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
摘要翻译：公开了一种用于减小密度失配的系统和方法。一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

19. 发明申请

US20110215420A1 CASCODE CMOS STRUCTURE 有权
标题翻译： CASCODE CMOS结构
公开(公告)号：US20110215420A1
公开(公告)日：2011-09-08
申请号：US12766972
申请日：2010-04-26
申请人： Fu-Lung HSUEH , Chih-Ping Chao , Chewn-Pu Jou , Yung-Chow Peng , Harry-Hak-Lay Chuang , Kuo-Tung Sung
发明人： Fu-Lung HSUEH , Chih-Ping Chao , Chewn-Pu Jou , Yung-Chow Peng , Harry-Hak-Lay Chuang , Kuo-Tung Sung
IPC分类号： H01L27/088 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/50 , G06F17/5009 , H01L27/088 , H01L27/0922
摘要： A MOS device includes an active area having first and second contacts. First and second gates are disposed between the first and second contacts. The first gate is disposed adjacent to the first contact and has a third contact. The second gate is disposed adjacent to the second contact and has a fourth contact coupled to the third contact. A transistor defined by the active area and the first gate has a first threshold voltage, and a transistor defined by the active area and the second gate has a second threshold voltage.
摘要翻译： MOS器件包括具有第一和第二触点的有源区。第一和第二栅极设置在第一和第二触点之间。第一门被设置成与第一接触相邻并且具有第三接触。第二栅极被设置成与第二触点相邻并且具有耦合到第三触点的第四触点。由有源区和第一栅极限定的晶体管具有第一阈值电压，并且由有源区和第二栅极限定的晶体管具有第二阈值电压。

20. 发明申请

US20090315743A1 Increasing 8B/10B Coding Speed Using a Disparity Look-Ahead Table 有权
标题翻译：增加8B / 10B编码速度使用视差前视表
公开(公告)号：US20090315743A1
公开(公告)日：2009-12-24
申请号：US12121509
申请日：2008-05-15
申请人： Wen-Hung Huang , Yung-Chow Peng
发明人： Wen-Hung Huang , Yung-Chow Peng
IPC分类号： H03M7/00
CPC分类号： H04L25/4908 , H04L25/4919
摘要： A method for encoding data packets includes providing an encoding scheme for coding source data units into encoded data units; establishing a first look-ahead table for the source data units; providing a data packet including a first source data unit and a second source data unit; encoding the first source data unit to generate a first encoded data unit; indexing the first look-ahead table using the first source data unit to determine a balancing capability of the first encoded data unit for balancing a running disparity; and encoding the second source data unit to generate a second encoded data unit using the balancing capability of the first encoded data unit.
摘要翻译：一种用于编码数据分组的方法包括提供用于将源数据单元编码为编码数据单元的编码方案; 为源数据单元建立第一个预先表; 提供包括第一源数据单元和第二源数据单元的数据分组; 编码所述第一源数据单元以生成第一编码数据单元; 使用所述第一源数据单元索引所述第一预览表，以确定所述第一编码数据单元的平衡能力以平衡运行的差异; 以及使用所述第一编码数据单元的平衡能力对所述第二源数据单元进行编码以生成第二编码数据单元。

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