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11. 发明申请

US20090238301A1 MULTILEVEL SIGNAL RECEIVER 审中-公开
标题翻译：多信号接收器
公开(公告)号：US20090238301A1
公开(公告)日：2009-09-24
申请号：US12407621
申请日：2009-03-19
申请人： Tszshing Cheung
发明人： Tszshing Cheung
IPC分类号： H04L25/34 , H04L25/49
CPC分类号： H04L25/063 , H04L25/4925
摘要： In the present multilevel signal receiver, an output signal of a comparator which judges a high-level of a multilevel signal and a signal obtained by inverting an output signal of a comparator which judges a low-level of the multilevel signal are input to an edge-triggered RS-FF, and an output signal of the edge-triggered RS-FF is fed back to the comparator on the high-level side via a LPF, so that a high-level threshold voltage is regulated. At the same time, a signal obtained by inverting the output signal of the comparator on the high-level side and the output signal of the comparator on the low-level side are input to an edge-triggered RS-FF, and an output signal of the edge-triggered RS-FF is fed back to the comparator on the low-level side via a LPF, so that a low-level threshold voltage is regulated. As a result, it becomes possible to provide a multilevel signal receiver of a simple circuit configuration, capable of controlling the thresholds used for level judgment of the multilevel signal of three or more levels to follow in real time a level change in the multilevel signal.
摘要翻译：在当前的多电平信号接收机中，判定多电平信号的高电平的比较器的输出信号和将判定多电平信号的低电平的比较器的输出信号反相得到的信号输入到边沿触发的RS-FF，边沿触发的RS-FF的输出信号通过LPF反馈到高电平侧的比较器，从而调节高电平阈值电压。同时，通过将高电平侧的比较器的输出信号和低电平侧的比较器的输出信号反相而获得的信号被输入到边沿触发的RS-FF，输出信号边沿触发的RS-FF通过LPF反馈到低电平侧的比较器，从而调节低电平阈值电压。结果，可以提供一种简单电路结构的多电平信号接收机，其能够控制用于三电平或更多电平的多电平信号的电平判断的阈值实时跟踪多电平信号中的电平变化。

12. 发明申请

US20070146014A1 Phase interpolator with adaptive delay adjustment 有权
标题翻译：具有自适应延迟调整的相位插值器
公开(公告)号：US20070146014A1
公开(公告)日：2007-06-28
申请号：US11489341
申请日：2006-07-19
申请人： Tszshing Cheung
发明人： Tszshing Cheung
IPC分类号： H03K5/19
CPC分类号： H03L7/081 , H03K2005/00052 , H03L7/091 , H04L7/0337
摘要： The phase interpolator includes two adjustable delays 30 and 31, phase comparator 32 which detects a phase difference between a signal delayed by the adjustable delay 30 and a signal delayed by the adjustable delay 31, an integrator 33 which integrates the outputs of the phase comparator 32 and multipliers 34-1 and 34-2 which set a control voltage for the adjustable delays 30 and 31. The feedback loop comprising phase comparator 32 and integrator 33 controls a delay amount of the adjustable delay 30 thereby securing a phase relation between {ACK1, ACK2} and ICK to achieve a stable ICK phase.
摘要翻译：相位插值器包括两个可调节延迟30和31，相位比较器32，其检测延迟了可调节延迟30的信号与由可调延迟31延迟的信号之间的相位差;积分器33，其对相位比较器32的输出进行积分以及为可调节延迟30和31设定控制电压的乘法器34-1和34-2。包括相位比较器32和积分器33的反馈回路控制可调节延迟30的延迟量，从而确保{ACK 1，ACK 2}和ICK之间的相位关系，以实现稳定的ICK相位。

13. 发明授权

US07816963B1 Phase interpolator with adaptive delay adjustment 有权
公开(公告)号：US07816963B1
公开(公告)日：2010-10-19
申请号：US12828779
申请日：2010-07-01
申请人： Tszshing Cheung
发明人： Tszshing Cheung
IPC分类号： H03L7/06
CPC分类号： H03L7/081 , H03K2005/00052 , H03L7/091 , H04L7/0337
摘要： The phase interpolator includes two adjustable delays 30 and 31, phase comparator 32 which detects a phase difference between a signal delayed by the adjustable delay 30 and a signal delayed by the adjustable delay 31, an integrator 33 which integrates the outputs of the phase comparator 32 and multipliers 34-1 and 34-2 which set a control voltage for the adjustable delays 30 and 31. The feedback loop comprising phase comparator 32 and integrator 33 controls a delay amount of the adjustable delay 30 thereby securing a phase relation between {ACK1, ACK2} and ICK to achieve a stable ICK phase.

14. 发明授权

US07629814B2 Latch circuit and deserializer circuit 有权
标题翻译：锁存电路和解串器电路
公开(公告)号：US07629814B2
公开(公告)日：2009-12-08
申请号：US11942922
申请日：2007-11-20
申请人： Tszshing Cheung
发明人： Tszshing Cheung
IPC分类号： H03K19/20
CPC分类号： H03K3/356139 , H03M9/00
摘要： A latch includes a precharging unit, a memory logic unit, an input amplifying unit, and a clock synchronization switch. The memory logic unit and the input amplifying unit are arranged in a same transistor level. Thus, the latch has three transistor levels. Further, a current supply 150 is connected to the memory logic unit to control a current flowing through the memory logic unit.
摘要翻译：锁存器包括预充电单元，存储器逻辑单元，输入放大单元和时钟同步开关。存储器逻辑单元和输入放大单元被布置在相同的晶体管级中。因此，锁存器具有三个晶体管级。此外，电流源150连接到存储器逻辑单元以控制流过存储器逻辑单元的电流。

15. 发明申请

US20090140773A1 Phase detection apparatus and phase synchronization apparatus 有权
标题翻译：相位检测装置和相位同步装置
公开(公告)号：US20090140773A1
公开(公告)日：2009-06-04
申请号：US12320494
申请日：2009-01-27
申请人： Tszshing Cheung
发明人： Tszshing Cheung
IPC分类号： H03D13/00 , H03L7/06
CPC分类号： H03L7/0891 , H03L7/091
摘要： A feedback circuit includes a third variable delay device that controls the amount of phase delay of a first clock; a third logic gate that detects a phase difference between the first clock delayed by the third variable delay device and the first clock, and outputs a third signal of a pulse width corresponding to the phase difference detected; and a LPF that outputs, as a control signal Vcontrol, the integral of the pulse width of the third signal. The control signal Vcontrol, indicative of a delay amount, is fed back the third variable delay device and input to a first variable delay device and a second variable delay device of a phase-difference detection unit.
摘要翻译：反馈电路包括控制第一时钟的相位延迟量的第三可变延迟器件; 第三逻辑门，其检测由所述第三可变延迟装置延迟的所述第一时钟与所述第一时钟之间的相位差，并输出与所检测的相位差对应的脉冲宽度的第三信号; 以及作为控制信号Vcontrol输出第三信号的脉冲宽度的积分的LPF。指示延迟量的控制信号Vcontrol被反馈到第三可变延迟装置，并输入到相位差检测单元的第一可变延迟装置和第二可变延迟装置。

16. 发明申请

US20080144399A1 LATCH CIRCUIT AND DESERIALIZER CIRCUIT 有权
标题翻译：绞线电路和电解电路
公开(公告)号：US20080144399A1
公开(公告)日：2008-06-19
申请号：US11942922
申请日：2007-11-20
申请人： Tszshing Cheung
发明人： Tszshing Cheung
IPC分类号： G11C7/00
CPC分类号： H03K3/356139 , H03M9/00
摘要： A latch includes a precharging unit, a memory logic unit, an input amplifying unit, and a clock synchronization switch. The memory logic unit and the input amplifying unit are arranged in a same transistor level. Thus, the latch has three transistor levels. Further, a current supply 150 is connected to the memory logic unit to control a current flowing through the memory logic unit.
摘要翻译：锁存器包括预充电单元，存储器逻辑单元，输入放大单元和时钟同步开关。存储器逻辑单元和输入放大单元被布置在相同的晶体管级中。因此，锁存器具有三个晶体管级。此外，电流源150连接到存储器逻辑单元以控制流过存储器逻辑单元的电流。

17. 发明授权

US07907078B2 Analog-to-digital converter and analog to-digital conversion method 有权
标题翻译：模数转换器和模数转换方式
公开(公告)号：US07907078B2
公开(公告)日：2011-03-15
申请号：US12620965
申请日：2009-11-18
申请人： Tszshing Cheung
发明人： Tszshing Cheung
IPC分类号： H03M1/34
CPC分类号： H03M1/38
摘要： An analog-to-digital converter is disclosed. An input signal processor sets a voltage of an input signal as an initial value of a signal voltage Vin, subtracts ½n of an input range from the nth (n is a positive integer) signal voltage based on a comparison result output from a comparator, and outputs the (n+1)th signal voltage. A reference voltage source outputs a reference voltage to be compared with the signal voltage output from the input signal processor, the reference voltage being obtained by repeatedly reducing by one half the input range. A comparator compares the signal voltage from the input signal processor with the reference voltage from the reference voltage source.
摘要翻译：公开了一种模拟 - 数字转换器。输入信号处理器将输入信号的电压设置为信号电压Vin的初始值，基于从比较器输出的比较结果从第n（n为正整数）信号电压减去输入范围的1/2，以及输出第（n + 1）个信号电压。参考电压源输出与输入信号处理器输出的信号电压进行比较的参考电压，参考电压通过反复减少输入范围的一半而获得。比较器将来自输入信号处理器的信号电压与参考电压源的参考电压进行比较。

18. 发明授权

US07675328B2 Phase detection apparatus and phase synchronization apparatus 有权
标题翻译：相位检测装置和相位同步装置
公开(公告)号：US07675328B2
公开(公告)日：2010-03-09
申请号：US12320494
申请日：2009-01-27
申请人： Tszshing Cheung
发明人： Tszshing Cheung
IPC分类号： H03D13/00
CPC分类号： H03L7/0891 , H03L7/091
摘要： A feedback circuit includes a third variable delay device that controls the amount of phase delay of a first clock; a third logic gate that detects a phase difference between the first clock delayed by the third variable delay device and the first clock, and outputs a third signal of a pulse width corresponding to the phase difference detected; and a LPF that outputs, as a control signal Vcontrol, the integral of the pulse width of the third signal. The control signal Vcontrol, indicative of a delay amount, is fed back the third variable delay device and input to a first variable delay device and a second variable delay device of a phase-difference detection unit.
摘要翻译：反馈电路包括控制第一时钟的相位延迟量的第三可变延迟器件; 第三逻辑门，其检测由所述第三可变延迟装置延迟的所述第一时钟与所述第一时钟之间的相位差，并输出与所检测的相位差对应的脉冲宽度的第三信号; 以及作为控制信号Vcontrol输出第三信号的脉冲宽度的积分的LPF。指示延迟量的控制信号Vcontrol被反馈到第三可变延迟装置，并输入到相位差检测单元的第一可变延迟装置和第二可变延迟装置。

19. 发明授权

US07595668B2 High speed dynamic frequency divider 有权
标题翻译：高速动态分频器
公开(公告)号：US07595668B2
公开(公告)日：2009-09-29
申请号：US11680841
申请日：2007-03-01
申请人： Tszshing Cheung
发明人： Tszshing Cheung
IPC分类号： H03B19/00
CPC分类号： H03K27/00 , H03K23/54
摘要： The frequency divider includes the buffer 30, the function selector 31 and the inverter 32. The output of the function selector 31 is input to the buffer 30. The output of the buffer 30 is fed back to the function selector 31 by two paths. One path includes the inverter 32 and the other does not. The function selector 31 selects one of the paths in synchronous with input clock CK. At one timing the output of the buffer 30 is flipped by the inverter 32. At the next timing the output of the buffer 30 is held the same by the function selector 31 selecting the path not including the inverter 32.
摘要翻译：分频器包括缓冲器30，功能选择器31和反相器32.功能选择器31的输出被输入到缓冲器30.缓冲器30的输出通过两条路径反馈到功能选择器31。一个路径包括逆变器32，另一个路径不包括逆变器32。功能选择器31选择与输入时钟CK同步的一个路径。在一个定时，缓冲器30的输出被反相器32翻转。在下一个定时，由选择不包括逆变器32的路径的功能选择器31使缓冲器30的输出保持相同。

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