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11. 发明授权

US07233527B2 Nonvolatile memory structure 有权
公开(公告)号：US07233527B2
公开(公告)日：2007-06-19
申请号：US11162730
申请日：2005-09-21
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/3468
摘要： The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.

12. 发明申请

US20050167731A1 Double-cell memory device 有权
标题翻译：双电池存储器件
公开(公告)号：US20050167731A1
公开(公告)日：2005-08-04
申请号：US10871170
申请日：2004-06-18
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C16/04 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7923
摘要： A memory array device has a plurality of gate structure lines, adjacently disposed over a substrate along a direction, wherein at least a portion of the gate structure lines have memory function. A plurality of first doped regions, in the substrate at a side of a first line of the gate structure lines. A plurality of second doped regions, in the substrate at a side of a last line of the gate structure lines. Wherein the first doped regions and the second doped regions respectively for a plurality of pairs of doped region with respect to a plurality of bit lines. In other words, the conventional source/drain regions for each memory cell are saved. Instead, the gate lines are adjacently disposed together.
摘要翻译：存储器阵列器件具有多个栅极结构线，沿着一个方向相邻地设置在衬底上，其中栅极结构线的至少一部分具有记忆功能。多个第一掺杂区域，在栅极结构线的第一条线的一侧的衬底中。在栅极结构线的最后一行的一侧的衬底中的多个第二掺杂区域。其中第一掺杂区和第二掺杂区相对于多个位线分别用于多对掺杂区。换句话说，每个存储单元的常规源/漏区被保存。相反，栅极线相邻地放置在一起。

13. 发明申请

US20050167730A1 Cell structure of nonvolatile memory device 审中-公开
标题翻译：非易失性存储器件的单元结构
公开(公告)号：US20050167730A1
公开(公告)日：2005-08-04
申请号：US10848592
申请日：2004-05-17
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C16/04 , H01L21/8246 , H01L27/115 , H01L29/76 , H01L29/792
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0483 , H01L27/115 , H01L29/792
摘要： The invention is directed to a nonvolatile memory device. Each memory cell is formed to have the depletion mode operation by doped opposite conductive-type dopants to the substrate at the surface region under the gate electrode, so that the depletion memory cell is formed. The charge-storing structure layer is, for example, an O/N/O structure layer, wherein the nitride layer is used to store the charge. The erasing operation speed can be improved.
摘要翻译：本发明涉及一种非易失性存储器件。每个存储单元被形成为具有通过在栅电极下方的表面区域向衬底掺杂的相对导电型掺杂剂的耗尽模式操作，从而形成耗尽存储单元。电荷存储结构层例如是O / N / O结构层，其中氮化物层用于存储电荷。可以提高擦除操作速度。

14. 发明授权

US07094649B2 Method for forming multi-level mask ROM cell and NAND multi-level mask ROM 有权
标题翻译：用于形成多电平掩模ROM单元和NAND多级掩模ROM的方法
公开(公告)号：US07094649B2
公开(公告)日：2006-08-22
申请号：US10886981
申请日：2004-07-07
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： H01L21/8236
CPC分类号： G11C11/5692 , G11C16/0483 , H01L27/112 , H01L27/1122 , H01L27/1126
摘要： The present invention relates to a multi-level read only memory cell that can store two bits and the fabrication method thereof. The multi-level ROM cell has the storage capacity of two bits and the resultant NAND type ROM memory array can provide four logic states of two bits, thus increasing the data storage capacity.
摘要翻译：本发明涉及可存储两位的多级只读存储器单元及其制造方法。多级ROM单元具有两位的存储容量，并且所得的NAND型ROM存储器阵列可以提供两位的四个逻辑状态，从而增加数据存储容量。

15. 发明授权

US07046549B2 Nonvolatile memory structure 有权
标题翻译：非易失性存储器结构
公开(公告)号：US07046549B2
公开(公告)日：2006-05-16
申请号：US10707665
申请日：2003-12-31
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C16/04
CPC分类号： G11C16/3468
摘要： The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.
摘要翻译：本发明涉及非易失性存储器件的布局。存储单元具有栅电极，第一掺杂电极和第二掺杂电极。第一掺杂电极耦合到位线。栅电极耦合到一个分离的字线。共享耦合电容器结构耦合在来自第二掺杂电极的相邻位线的所有存储单元之间。电容器结构具有至少两个浮栅MOS电容器。每个浮栅MOS电容器具有浮置晶体管，其具有浮置栅极，第一S / D区域和第二S / D区域; 以及耦合到浮动栅极的MOS电容器。第一S / D区域耦合到相应一个晶体管存储单元的第二掺杂电极，并且第二S / D区域与浮置栅晶体管的相邻一个共享。

16. 发明申请

US20060067118A1 NONVOLATILE MEMORY STRUCTURE 有权
标题翻译：非易失性存储器结构
公开(公告)号：US20060067118A1
公开(公告)日：2006-03-30
申请号：US11162731
申请日：2005-09-21
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C16/04
CPC分类号： G11C16/3468
摘要： The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.
摘要翻译：本发明涉及非易失性存储器件的布局。存储单元具有栅电极，第一掺杂电极和第二掺杂电极。第一掺杂电极耦合到位线。栅电极耦合到一个分离的字线。共享耦合电容器结构耦合在来自第二掺杂电极的相邻位线的所有存储单元之间。电容器结构具有至少两个浮栅MOS电容器。每个浮栅MOS电容器具有浮置晶体管，其具有浮置栅极，第一S / D区域和第二S / D区域; 以及耦合到浮动栅极的MOS电容器。第一S / D区域耦合到相应一个晶体管存储单元的第二掺杂电极，并且第二S / D区域与浮置栅晶体管的相邻一个共享。

17. 发明申请

US20050170589A1 Method for forming mask ROM 审中-公开
标题翻译：掩模ROM形成方法
公开(公告)号：US20050170589A1
公开(公告)日：2005-08-04
申请号：US10886784
申请日：2004-07-07
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： H01L21/336 , H01L21/8236 , H01L21/8246 , H01L27/112
CPC分类号： H01L27/1122 , H01L27/112 , H01L27/1126
摘要： The present invention relates to a fabrication method for a mask read only memory structure. By forming double spacers, the code implantation can be performed in a self-aligned way into the channel regions of predetermined memory cells. By avoiding erroneous implantation to the non-channel regions and thus the laterally diffusion of the un-wanted impurities to the channel regions of non-coded memory cells, the threshold voltage of the non-coded memory cells can be unaffected and the error rate of reading can be greatly reduced.
摘要翻译：本发明涉及一种掩模只读存储器结构的制造方法。通过形成双重间隔物，代码注入可以以自对准的方式进行到预定存储器单元的沟道区域中。通过避免错误地植入非沟道区域，从而将不需要的杂质横向扩散到非编码存储器单元的沟道区域，非编码存储器单元的阈值电压可以不受影响，并且误差率阅读可以大大减少。

18. 发明授权

US07200038B2 Nonvolatile memory structure 有权
标题翻译：非易失性存储器结构
公开(公告)号：US07200038B2
公开(公告)日：2007-04-03
申请号：US11162731
申请日：2005-09-21
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3468
摘要： The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.
摘要翻译：本发明涉及非易失性存储器件的布局。存储单元具有栅电极，第一掺杂电极和第二掺杂电极。第一掺杂电极耦合到位线。栅电极耦合到一个分离的字线。共享耦合电容器结构耦合在来自第二掺杂电极的相邻位线的所有存储单元之间。电容器结构具有至少两个浮栅MOS电容器。每个浮栅MOS电容器具有浮置晶体管，其具有浮置栅极，第一S / D区域和第二S / D区域; 以及耦合到浮动栅极的MOS电容器。第一S / D区域耦合到相应一个晶体管存储单元的第二掺杂电极，并且第二S / D区域与浮置栅晶体管的相邻一个共享。

19. 发明申请

US20060067124A1 NONVOLATILE MEMORY STRUCTURE 有权
公开(公告)号：US20060067124A1
公开(公告)日：2006-03-30
申请号：US11162730
申请日：2005-09-21
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： G11C16/04
CPC分类号： G11C16/3468
摘要： The invention is directed to a layout of nonvolatile memory device. The memory cell has a gate electrode, a first doped electrode, and a second doped electrode. The first doped electrode is coupled to the bit line. The gate electrode is coupled to one separated word line. A shared coupled capacitor structure is coupled between all of memory cells of the adjacent bit lines from the second doped electrode. The capacitor structure has at least two floating-gate MOS capacitors. Each floating-gate MOS capacitor has a floating-gate transistor having a floating gate, a first S/D region and a second S/D region; and a MOS capacitor coupled to the floating gate. The first S/D region is coupled to the second doped electrode of the corresponding one of the transistor memory cells, and the second S/D region is shared with an adjacent one of the floating-gate transistor.

20. 发明授权

US06987298B2 Circuit layout and structure for a non-volatile memory 有权
标题翻译：非易失性存储器的电路布局和结构
公开(公告)号：US06987298B2
公开(公告)日：2006-01-17
申请号：US10823488
申请日：2004-04-12
申请人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
发明人： Chien-Hsing Lee , Chin-Hsi Lin , Jhyy-Cheng Liou
IPC分类号： H01L29/792
CPC分类号： G11C16/0491 , G11C16/0475 , H01L27/115 , H01L27/11568 , H01L29/42328 , H01L29/42344 , H01L29/7887 , H01L29/7923
摘要： A structure of non-volatile memory contains a substrate. A plurality of bit lines are formed in the substrate along a first direction, wherein each of the bit lines also serve as a source/drain (S/D) region. A first dielectric layer is disposed over the substrate. A plurality of selection gate (SG) lines are formed over the first dielectric layer between the bit lines. A plurality of charge-storage structure layer are formed over the substrate between the bit lines and the SG lines. A second dielectric layer is formed over the SG lines and a third dielectric layer is formed over the bit lines. A plurality of word lines are formed over the substrate along a second direction, which is crossing the first direction for the bit lines. Wherein, when a selected one of the SG lines is applied a voltage, another S/D region is created in the substrate under the selected one of the SG lines.
摘要翻译：非易失性存储器的结构包含衬底。沿着第一方向在衬底中形成多个位线，其中每个位线还用作源极/漏极（S / D）区域。第一电介质层设置在衬底上。在位线之间的第一电介质层上形成多个选择栅（SG）线。在位线和SG线之间的衬底上形成多个电荷存储结构层。在SG线上形成第二电介质层，并且在位线之上形成第三介电层。沿着与位线的第一方向交叉的第二方向在基板上形成多个字线。其中，当所选择的一条SG线施加电压时，在所选择的一条SG线之下的衬底中产生另一S / D区。

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