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11. 发明授权

US10629681B2 III-nitride devices including a graded depleting layer 有权
公开(公告)号：US10629681B2
公开(公告)日：2020-04-21
申请号：US16287211
申请日：2019-02-27
申请人： Transphorm Inc.
发明人： Umesh Mishra , Rakesh K. Lal , Geetak Gupta , Carl Joseph Neufeld , David Rhodes
IPC分类号： H01L29/00 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/778 , H01L29/872 , H01L29/20 , H01L29/205 , H01L29/40 , H01L29/10 , H01L23/495
CPC分类号： H01L29/0688 , H01L29/0619 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/66462 , H01L29/7785 , H01L29/7786 , H01L29/872 , H01L23/49562 , H01L29/1066 , H01L29/1075
摘要： A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.

12. 发明授权

US10224401B2 III-nitride devices including a graded depleting layer 有权
公开(公告)号：US10224401B2
公开(公告)日：2019-03-05
申请号：US15564498
申请日：2017-05-31
申请人： Transphorm Inc.
发明人： Umesh Mishra , Rakesh K. Lal , Geetak Gupta , Carl Joseph Neufeld , David Rhodes
IPC分类号： H01L29/00 , H01L23/495 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/778 , H01L29/872 , H01L29/20 , H01L29/205 , H01L29/40 , H01L29/10
摘要： A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.

13. 发明授权

US10199217B2 Methods of forming reverse side engineered III-nitride devices 有权
公开(公告)号：US10199217B2
公开(公告)日：2019-02-05
申请号：US15288120
申请日：2016-10-07
申请人： Transphorm Inc.
发明人： Rongming Chu , Umesh Mishra , Rakesh K. Lal
IPC分类号： H01L29/06 , H01L21/02 , H01L29/20 , H01L29/417 , H01L29/66 , H01L29/778 , H01L29/861 , H01L23/29 , H01L23/31 , H01L29/423 , H01L23/00
摘要： Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

14. 发明授权

US09490324B2 N-polar III-nitride transistors 有权
公开(公告)号：US09490324B2
公开(公告)日：2016-11-08
申请号：US14744526
申请日：2015-06-19
申请人： Transphorm Inc.
发明人： Umesh Mishra , Srabanti Chowdhury , Carl Joseph Neufeld
IPC分类号： H01L29/66 , H01L29/10 , H01L29/205 , H01L29/78 , H01L29/778 , H01L29/20 , H01L29/04
CPC分类号： H01L29/1054 , H01L29/045 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7781 , H01L29/7785 , H01L29/78
摘要： An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.

15. 发明申请

US20160254363A1 GALLIUM NITRIDE POWER DEVICES 审中-公开
公开(公告)号：US20160254363A1
公开(公告)日：2016-09-01
申请号：US15149467
申请日：2016-05-09
申请人： Transphorm Inc.
发明人： Chang Soo Suh , Umesh Mishra
IPC分类号： H01L29/66 , H01L29/778 , H01L29/40 , H01L29/417 , H01L29/10 , H01L29/20
CPC分类号： H01L29/66462 , H01L29/1066 , H01L29/1075 , H01L29/2003 , H01L29/402 , H01L29/41766 , H01L29/432 , H01L29/778 , H01L29/7781 , H01L29/7783 , H01L29/7787
摘要： Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.

16. 发明授权

US09318593B2 Forming enhancement mode III-nitride devices 有权
标题翻译：形成增强型III族氮化物器件
公开(公告)号：US09318593B2
公开(公告)日：2016-04-19
申请号：US14542937
申请日：2014-11-17
申请人： Transphorm Inc.
发明人： Mo Wu , Rakesh K. Lal , Ilan Ben-Yaacov , Umesh Mishra , Carl Joseph Neufeld
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/7787 , H01L21/02241 , H01L21/02255 , H01L21/28264 , H01L21/30617 , H01L21/30621 , H01L21/3081 , H01L21/31144 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/4232 , H01L29/4236 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/7783 , H01L29/7786
摘要： A method of fabricating a III-N device includes forming a III-N channel layer on a substrate, a III-N barrier layer on the channel layer, an insulator layer on the barrier layer, and a trench in a first portion of the device. Forming the trench comprises removing the insulator layer and a part of the barrier layer in the first portion of the device, such that a remaining portion of the barrier layer in the first portion of the device has a thickness away from a top surface of the channel layer, the thickness being within a predetermined thickness range, annealing the III-N device in a gas ambient including oxygen at an elevated temperature to oxidize the remaining portion of the barrier layer in the first portion of the device, and removing the oxidized remaining portion of the barrier layer in the first portion of the device.
摘要翻译：制造III-N器件的方法包括在衬底上形成III-N沟道层，在沟道层上形成III-N势垒层，在阻挡层上形成绝缘体层，在器件的第一部分形成沟槽。形成沟槽包括在器件的第一部分中去除绝缘体层和阻挡层的一部分，使得器件的第一部分中的阻挡层的剩余部分具有远离沟道顶表面的厚度层，厚度在预定厚度范围内，在包括氧气的气体环境中在升高的温度下退火III-N器件以氧化器件的第一部分中的阻挡层的剩余部分，并且去除氧化的剩余部分在装置的第一部分中的阻挡层。

17. 发明申请

US20160064495A1 SEMICONDUCTOR DEVICES WITH INTEGRATED HOLE COLLECTORS 有权
标题翻译：具有集成孔收集器的半导体器件
公开(公告)号：US20160064495A1
公开(公告)日：2016-03-03
申请号：US14934565
申请日：2015-11-06
申请人： Transphorm Inc.
发明人： Umesh Mishra , Srabanti Chowdhury , Ilan Ben-Yaacov
IPC分类号： H01L29/40 , H01L29/20 , H01L29/207 , H01L29/78
CPC分类号： H01L29/402 , H01L29/0619 , H01L29/2003 , H01L29/207 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/7786 , H01L29/78
摘要： Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.
摘要翻译：描述了包括具有集成的空穴集电区域的半导体层的晶体管器件。空穴集电极区域被配置为在操作期间收集在晶体管器件中产生的空穴并且将它们远离器件的有源区域传送。空穴集电极区域可以电连接或耦合到器件的源极，漏极或场板。空穴集电极区域可以被掺杂，例如p型或名义上的p型，并且能够导通空穴而不是电子。

18. 发明申请

US20150333147A1 TRANSISTORS WITH ISOLATION REGIONS 有权
标题翻译：具有隔离区的晶体管
公开(公告)号：US20150333147A1
公开(公告)日：2015-11-19
申请号：US14810906
申请日：2015-07-28
申请人： Transphorm Inc.
发明人： Umesh Mishra , Srabanti Chowdhury
IPC分类号： H01L29/66 , H01L29/423 , H01L29/40 , H01L29/06 , H01L29/20
CPC分类号： H01L29/66462 , H01L29/0649 , H01L29/0657 , H01L29/2003 , H01L29/207 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/778 , H01L29/7786 , H01L2924/0002 , H01L2924/00
摘要： A transistor device is described that includes a source, a gate, a drain, a semiconductor material which includes a gate region between the source and the drain, a plurality of channel access regions in the semiconductor material on either side of the gate, a channel in the semiconductor material having an effective width in the gate region and in the channel access regions, and an isolation region in the gate region. The isolation region serves to reduce the effective width of the channel in the gate region without substantially reducing the effective width of the channel in the access regions. Alternatively, the isolation region can be configured to collect holes that are generated in the transistor device. The isolation region may simultaneously achieve both of these functions.
摘要翻译：描述了一种晶体管器件，其包括源极，栅极，漏极，包括源极和漏极之间的栅极区域的半导体材料，栅极两侧的半导体材料中的多个沟道存取区域，沟道在栅极区域和沟道存取区域中具有有效宽度的半导体材料以及栅极区域中的隔离区域。隔离区域用于减小栅极区域中的沟道的有效宽度，而基本上不会减小通路区域中的通道的有效宽度。或者，隔离区域可以被配置为收集在晶体管器件中产生的空穴。隔离区域可以同时实现这两个功能。

19. 发明授权

US09171836B2 Method of forming electronic components with increased reliability 有权
标题翻译：形成电子元件的可靠性提高的方法
公开(公告)号：US09171836B2
公开(公告)日：2015-10-27
申请号：US14478504
申请日：2014-09-05
申请人： Transphorm Inc.
发明人： Rakesh K. Lal , Robert Coffie , Yifeng Wu , Primit Parikh , Yuvaraj Dora , Umesh Mishra , Srabanti Chowdhury , Nicholas Fichtenbaum
IPC分类号： H03K17/687 , H01L27/02 , H01L25/00 , H01L21/8236 , H01L27/06 , H01L49/02 , H01L29/778 , H03K17/10 , H01L29/423 , H01L29/872 , H01L29/20
CPC分类号： H01L27/0288 , H01L21/8236 , H01L25/00 , H01L27/0629 , H01L28/20 , H01L29/2003 , H01L29/42376 , H01L29/4238 , H01L29/7786 , H01L29/872 , H01L2924/0002 , H03K17/102 , H03K2017/6875 , Y10T29/49117 , H01L2924/00
摘要： An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.
摘要翻译：电子部件包括耗尽型晶体管，增强型晶体管和电阻。耗尽型晶体管具有比增强型晶体管更高的击穿电压。电阻器的第一端子电连接到增强型晶体管的源极，并且电阻器的第二端子和耗尽型晶体管的源极电连接到增强型晶体管的漏极。耗尽型晶体管的栅极可以电连接到增强型晶体管的源极。

20. 发明申请

US20150287785A1 N-POLAR III-NITRIDE TRANSISTORS 有权
标题翻译： N-极III型氮化物晶体管
公开(公告)号：US20150287785A1
公开(公告)日：2015-10-08
申请号：US14744526
申请日：2015-06-19
申请人： Transphorm Inc.
发明人： Umesh Mishra , Srabanti Chowdhury , Carl Joseph Neufeld
IPC分类号： H01L29/10 , H01L29/20 , H01L29/04 , H01L29/66
CPC分类号： H01L29/1054 , H01L29/045 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7781 , H01L29/7785 , H01L29/78
摘要： An N-polar III-N transistor includes a III-N buffer layer, a first III-N barrier layer, and a III-N channel layer, the III-N channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first III-N barrier layer and the III-N channel layer causes a conductive channel to be induced in the access regions of the III-N channel layer. The transistor also includes a source, a gate, a drain, and a second III-N barrier layer between the gate and the III-N channel layer. The second III-N barrier layer has an N-face proximal to the gate and a group-III face opposite the N-face, and has a larger bandgap than the III-N channel layer. The lattice constant of the first III-N barrier layer is within 0.5% of the lattice constant of the buffer layer.
摘要翻译： N极III-N晶体管包括III-N缓冲层，第一III-N势垒层和III-N沟道层，III-N沟道层具有栅极区域和相对的多个访问区域门区域两侧。第一III-N势垒层和III-N沟道层之间的组成差异导致在III-N沟道层的访问区域中引起导电沟道。晶体管还包括栅极和III-N沟道层之间的源极，栅极，漏极和第二III-N势垒层。第二III-N阻挡层具有靠近栅极的N面和与N面相对的III族面，并且具有比III-N沟道层更大的带隙。第一III-N势垒层的晶格常数在缓冲层的晶格常数的0.5％以内。

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