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11. 发明授权

US07421567B2 Using a modified value GPR to enhance lookahead prefetch 失效
标题翻译：使用修改值GPR来增强前瞻预取
公开(公告)号：US07421567B2
公开(公告)日：2008-09-02
申请号：US11016206
申请日：2004-12-17
申请人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Benjamin Walter Stolt , Brian William Thompto
发明人： Richard James Eickemeyer , Hung Qui Le , Dung Quoc Nguyen , Benjamin Walter Stolt , Brian William Thompto
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3842 , G06F9/3804 , G06F9/383 , G06F9/3838
摘要： The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microprocessor or thread of execution to be idle. The execution of such future instructions can initiate a prefetch of data or instructions from a distant cache or main memory, or otherwise make forward progress through the instruction stream. In this manner, when the instructions are re-executed (non speculatively executed) after the stall condition expires, they will execute with a reduced execution latency; e.g. by accessing data prefetched into the L1 cache, or enroute to the processor, or by executing the target instructions following a speculatively resolved mispredicted branch. In speculative mode, instruction operands may be invalid due to source loads that miss the L1 cache, facilities not available in speculative execution mode, or due to speculative instruction results that are not available. Dependency and dirty (i.e. invalid result) bits are tracked and used to determine which speculative instructions are valid for execution. A modified value register storage and bit vector are used to improve the availability of speculative results that would otherwise be discarded once they leave the execution pipeline because they cannot be written to the architected registers. The modified general purpose registers are used to store speculative results when the corresponding instruction reaches writeback and the modified bit vector tracks the results that have been stored there. Younger speculative instructions that do not bypass directly from older instructions will then use this modified data when the corresponding bit in the modified bit vector indicates the data has been modified. Otherwise, data from the architected registers will be used.
摘要翻译：本发明允许微处理器在失速状态期间识别和推测地执行未来的指令。这允许在停顿条件期间通过指令流进行正向进展，否则将导致微处理器或执行线程空闲。这样的未来指令的执行可以启动来自远程高速缓存或主存储器的数据或指令的预取，或以其他方式通过指令流进行进展。以这种方式，当在停止条件到期之后重新执行（不推测地执行）指令时，它们将以降低的执行延迟执行; 例如通过访问预取到L1高速缓存中的数据，或者进入处理器，或通过在推测性地解决的误预测分支之后执行目标指令。在推测模式中，由于缺少L1缓存的源加载，在推测执行模式下不可用的设备，或由于不可用的推测指令结果，指令操作数可能无效。跟踪依赖关系和脏（即无效结果）位，并用于确定哪些推测指令对执行有效。改进的值寄存器存储和位向量被用于提高推测结果的可用性，否则，由于不能将其写入到架构化的寄存器，否则将抛弃执行流水线。修改后的通用寄存器用于在对应指令到达回写时存储推测结果，修改后的位向量跟踪存储在其中的结果。当修改的位向量中的相应位指示数据已被修改时，不直接从旧指令旁路的较小的推测指令将使用该修改的数据。否则，将使用来自架构化寄存器的数据。

12. 发明授权

US07302553B2 Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue 有权
标题翻译：用于快速确定非移动指令队列中最旧指令的装置，系统和方法
公开(公告)号：US07302553B2
公开(公告)日：2007-11-27
申请号：US10351556
申请日：2003-01-23
申请人： Sam Gat-Shang Chu , Hung Qui Le , Dung Quoc Nguyen
发明人： Sam Gat-Shang Chu , Hung Qui Le , Dung Quoc Nguyen
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： An apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue of a processor are provided. Particularly, instructions are stored, one at a time at a clock cycle, in the non-moving queue. At every clock cycle, a present status of the instructions in the queue is recorded. Using the present status of the instructions in the queue in conjunction with previously recorded statuses of the instructions, the oldest instruction in the queue is determined. The status of the instructions in the queue includes whether or not the instruction has been issued for execution as well as whether or not it is known that the issued instruction has been accepted for execution.
摘要翻译：提供了一种用于快速确定处理器的非移动指令队列中的最旧指令的装置，系统和方法。特别地，在不移动队列中，以时钟周期一次存储指令。在每个时钟周期，记录队列中的指令的当前状态。结合队列中的指令的当前状态结合先前记录的指令状态，确定队列中最早的指令。队列中的指令的状态包括是否已经发出指令执行，以及是否知道发出的指令已被接受执行。

13. 发明授权

US07237094B2 Instruction group formation and mechanism for SMT dispatch 失效
标题翻译： SMT派遣指导小组组织和机制
公开(公告)号：US07237094B2
公开(公告)日：2007-06-26
申请号：US10965143
申请日：2004-10-14
申请人： Brian William Curran , Brian R. Konigsburg , Hung Qui Le , David Arnold Luick , Dung Quoc Nguyen
发明人： Brian William Curran , Brian R. Konigsburg , Hung Qui Le , David Arnold Luick , Dung Quoc Nguyen
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/30145 , G06F9/382 , G06F9/3851 , G06F9/3885
摘要： A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating resource requirements for merging two or more program instructions based on their resource fields, and determining resource availability for simultaneously executing the merged program instructions based on the calculated resource requirements. Resource vectors indicative of the required resource may be encoded into the resource fields, and the resource fields decoded at a later stage to derive the resource vectors. The resource fields can be stored in the instruction cache associated with the respective program instructions. The processor may operate in a simultaneous multithreading mode with different program instructions being part of different hardware threads. When the resource availability equals or exceeds the resource requirements for a group of instructions, those instructions can be dispatched simultaneously to the hardware resources. A start bit may be inserted in one of the program instructions to define the instruction group. The hardware resources may in particular be execution units such as a fixed-point unit, a load/store unit, a floating-point unit, or a branch processing unit.
摘要翻译：通过将资源字段与相应的程序指令相关联来处理计算机处理器中的指令的更有效的方法，其中资源字段指示需要哪个处理器硬件资源来执行程序指令，计算用于合并两个或多个程序指令的资源需求并且基于所计算的资源需求来确定用于同时执行所合并的程序指令的资源可用性。指示所需资源的资源矢量可以被编码到资源字段中，并且在稍后阶段解码资源字段以导出资源向量。资源字段可以存储在与相应的程序指令相关联的指令高速缓存中。处理器可以以同时多线程模式操作，其中不同的程序指令是不同硬件线程的一部分。当资源可用性等于或超过一组指令的资源需求时，可以将这些指令同时发送到硬件资源。可以在程序指令之一中插入起始位以定义指令组。硬件资源可以特别地是诸如定点单元，加载/存储单元，浮点单元或分支处理单元之类的执行单元。

14. 发明授权

US06658534B1 Mechanism to reduce instruction cache miss penalties and methods therefor 失效
标题翻译：降低指令高速缓存的机制错误惩罚及其方法
公开(公告)号：US06658534B1
公开(公告)日：2003-12-02
申请号：US09052247
申请日：1998-03-31
申请人： Steven Wayne White , Hung Qui Le , Kurt Alan Feiste , Paul Joseph Jordan
发明人： Steven Wayne White , Hung Qui Le , Kurt Alan Feiste , Paul Joseph Jordan
IPC分类号： G06F1200
CPC分类号： G06F9/382 , G06F9/3804 , G06F12/0862
摘要： The mechanism to reduce instruction cache miss penalties by initiating an early cache line prefetch is implemented. The mechanism provides for an early prefetch of a next succeeding cache line before an instruction cache miss is detected during a fetch which causes an instruction cache miss. The prefetch is initiated when it is guaranteed that instructions in the subsequent cache line will be referenced. This occurs when the current instruction is either a non-branch instruction, so instructions will execute sequentially, or if the current instruction is a branch instruction, but the branch forward is sufficiently short. If the current instruction is a branch, but the branch forward is to the next sequential cache line, a prefetch of the next sequential cache line may be performed. In this way, cache miss latencies may be reduced without generating cache pollution due to the prefetch of cache lines which are subsequently unreferenced.
摘要翻译：实现了通过启动早期高速缓存行预取来减少指令高速缓存未达错误的机制。该机制在提取期间检测到指令高速缓存未命中导致指令高速缓存未命中之前提供对下一个后续高速缓存行的早期预取。当保证将引用后续高速缓存行中的指令时，启动预取。当当前指令是非分支指令时，会发生这种情况，因此指令将顺序执行，或者当前指令是分支指令，但分支前进足够短。如果当前指令是分支，而分支转发到下一个顺序高速缓存行，则可以执行下一个顺序高速缓存行的预取。以这种方式，可以减少高速缓存未命中延迟，而不会由于先前未被引用的高速缓存线的预取而产生高速缓存污染。

15. 发明授权

US6061777A Apparatus and method for reducing the number of rename registers required in the operation of a processor 失效
标题翻译：用于减少处理器操作所需的重命名寄存器的数量的装置和方法
公开(公告)号：US6061777A
公开(公告)日：2000-05-09
申请号：US959646
申请日：1997-10-28
申请人： Hoichi Cheong , Paul Joseph Jordan , Hung Qui Le , Soummya Mallick
发明人： Hoichi Cheong , Paul Joseph Jordan , Hung Qui Le , Soummya Mallick
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3863 , G06F9/384
摘要： One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently architected RMAP entry for the architectural register targeted by the dispatched instruction; selecting the RMAP entries which are associated with physical registers that contain operands for the dispatched instruction; updating a use indicator in the selected RMAP entries; determining whether the dispatched instruction is interruptible; and updating an architectural indicator and a historical indicator in the presently architected RMAP entry if the dispatched instruction is uninterruptible.
摘要翻译：本发明的一个方面涉及一种用于操作处理器的方法。在本发明的一个版本中，该方法包括发送指令的步骤; 确定由发送的指令所针对的架构寄存器的目前架构化的RMAP条目; 选择与包含调度指令的操作数的物理寄存器相关联的RMAP条目; 更新所选RMAP条目中的使用指示符; 确定发送的指令是否可中断; 以及如果所分派的指令是不间断的，则更新当前架构的RMAP条目中的架构指示符和历史指示符。

16. 发明授权

US5983341A Data processing system and method for extending the time for execution of an instruction 失效
标题翻译：用于延长执行指令的时间的数据处理系统和方法
公开(公告)号：US5983341A
公开(公告)日：1999-11-09
申请号：US840921
申请日：1997-04-25
申请人： Hoichi Cheong , Paul Joseph Jordan , Hung Qui Le
发明人： Hoichi Cheong , Paul Joseph Jordan , Hung Qui Le
IPC分类号： G06F9/38 , G06F9/06 , G06F9/22
CPC分类号： G06F9/3836 , G06F9/3855
摘要： A data processing system indicates that an instruction does not have available data because of a cache miss or because of a non-cache-miss delay. When the instruction is not able to access the available data and a cache miss results, instructions which are dependent on the issued instruction are not issued. However, if the load execution is delayed because of a non-cache-miss delay, then the instructions which are dependent on the issued instruction are also issued in anticipation of a successful load instruction execution in a next timing cycle. Through the use of this issuing mechanism, the efficiency of the data processing system is increased as an execution unit is better able to utilize its pipeline.
摘要翻译：数据处理系统指示由于缓存未命中或由于非高速缓存未命中延迟而导致指令没有可用数据。当指令不能访问可用数据并且高速缓存未命中时，不发出取决于发出的指令的指令。然而，如果由于非高速缓存未命中延迟而导致负载执行被延迟，那么取决于所发出的指令的指令也是在下一个定时周期中预期成功的加载指令执行的情况下发出的。通过使用这种发布机制，随着执行单元更好地利用其管道，数据处理系统的效率得到提高。

17. 发明授权

US5875326A Data processing system and method for completing out-of-order instructions 失效
标题翻译：数据处理系统和完成无序指令的方法
公开(公告)号：US5875326A
公开(公告)日：1999-02-23
申请号：US840919
申请日：1997-04-25
申请人： Hoichi Cheong , Paul Joseph Jordan , Hung Qui Le
发明人： Hoichi Cheong , Paul Joseph Jordan , Hung Qui Le
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3842 , G06F9/3857
摘要： During operation of a pipelined data processing system, an interruptible instruction table is used to store target identifiers associated with instructions which may result in speculative execution. During operation of the interruptible instruction table, a pointer, referred to as a completing instruction buffer entry pointer, points to a bottom of the interruptible instruction table if that table includes any instruction. An entry at the bottom of the interruptible instruction table is a next instruction to complete. This entry includes a target identifier, referred to as a non-speculative-non-interruptible TID, may be used to release resources held for all prior executed instructions. The data processing system determines the value of the non-speculative-non-interruptible TID to ensure that order determination is preserved and provides a true speculative execution point.
摘要翻译：在流水线数据处理系统的操作期间，可中断指令表用于存储与可能导致推测执行的指令相关联的目标标识符。在可中断指令表的操作期间，如果该表包括任何指令，则称为完成指令缓冲器入口指针的指针指向可中断指令表的底部。可中断指令表底部的条目是要完成的下一条指令。该条目包括被称为不推测不可中断的TID的目标标识符可用于释放为所有先前执行的指令保持的资源。数据处理系统确定非推测不可中断TID的值，以确保顺序确定被保留并提供真实的推测执行点。

18. 发明授权

US5822752A Method and apparatus for fast parallel determination of queue entries 失效
标题翻译：用于快速并行确定队列条目的方法和装置
公开(公告)号：US5822752A
公开(公告)日：1998-10-13
申请号：US680745
申请日：1996-07-15
申请人： Hoichi Cheong , Michael Kevin Ciraula , Hung Qui Le , John Stephen Muhich
发明人： Hoichi Cheong , Michael Kevin Ciraula , Hung Qui Le , John Stephen Muhich
IPC分类号： G06F12/02 , G06F7/78 , G06F12/00 , G06F13/00
CPC分类号： G06F7/785
摘要： The present invention is related to a circuit useful to manage a random order queue having a plurality of queue entries, each queue entry having an associated validity bit which indicates whether the queue entry contains valid data. In one embodiment, the circuit includes a first plurality of inputs for receiving validity signals responsive to a first group of validity bits, a second plurality of inputs for receiving shift signals responsive to a second group of validity bits, and a plurality of outputs for providing select signals to multiplexers coupled to the queue, the select signals being responsive to the shift signals and the validity signals.
摘要翻译：本发明涉及一种用于管理具有多个队列条目的随机顺序队列的电路，每个队列条目具有指示队列条目是否包含有效数据的相关联的有效位。在一个实施例中，电路包括用于响应于第一组有效位的接收有效信号的第一多个输入端，用于响应于第二组有效位而接收移位信号的第二多个输入端，以及用于提供选择耦合到队列的复用器的信号，所述选择信号响应于移位信号和有效信号。

19. 发明授权

US08418180B2 Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors 失效
标题翻译：线程优先级方法，用于确保同时多线程微处理器的处理公平性
公开(公告)号：US08418180B2
公开(公告)日：2013-04-09
申请号：US12129876
申请日：2008-05-30
申请人： James Wilson Bishop , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy , Brian William Thompto , Raymond Cheung Yeung
发明人： James Wilson Bishop , Hung Qui Le , Dung Quoc Nguyen , Balaram Sinharoy , Brian William Thompto , Raymond Cheung Yeung
IPC分类号： G06F9/46
CPC分类号： G06F9/30101 , G06F9/3834 , G06F9/3851 , G06F9/3861 , G06F9/3885 , G06F9/4818 , G06F9/485
摘要： A method, apparatus, and computer program product are disclosed for ensuring processing fairness in simultaneous multi-threading (SMT) microprocessors. A clock cycle priority is assigned to a first thread and to a second thread during a standard selection state that lasts for an expected number of clock cycles by selecting the first thread to be a primary thread and the second thread to be a secondary thread. If a condition exists that requires overriding, an override state is executed by selecting the second thread to be the primary thread and the first thread to be the secondary thread. The override state is forced to be executed for an override period of time which equals the expected number of clock cycles plus a forced number of clock cycles. The forced number of clock cycles is granted to the first thread in response to the first thread again becoming the primary thread.
摘要翻译：公开了一种用于确保同时多线程（SMT）微处理器中的处理公平性的方法，装置和计算机程序产品。在通过选择作为主线程的第一线程和第二线程成为辅线程的持续期望的时钟周期数的标准选择状态期间，将时钟周期优先级分配给第一线程和第二线程。如果存在需要覆盖的条件，则通过选择作为主线程的第二个线程和第一个线程作为辅助线程来执行覆盖状态。超时状态被强制执行超时时间等于预期的时钟周期数加上强制的时钟周期数。响应于第一个线程再次成为主线程，强制的时钟周期数被授予第一个线程。

20. 发明申请

US20090063898A1 Processor Instruction Retry Recovery 失效
标题翻译：处理器指令重试恢复
公开(公告)号：US20090063898A1
公开(公告)日：2009-03-05
申请号：US12270300
申请日：2008-11-13
申请人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
发明人： Susan Elizabeth Eisen , Hung Qui Le , Michael James Mack , Dung Quoc Nguyen , Jose Angel Paredes , Scott Barnett Swaney
IPC分类号： G06F11/20
CPC分类号： G06F12/0888 , G06F9/30043 , G06F9/3851 , G06F9/3863 , G06F11/1407
摘要： Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution.
摘要翻译：恢复电路通过在停止处理器核心的检查点或备份进程之前等待任何挂起的存储条件指令或高速缓存禁止负载的无差错完成来响应处理器内核中的错误。恢复电路将处理器核从对称多处理器系统的逻辑配置中移除，可能会将错误的传播减少到系统的其他部分。处理器内核被复位，检查点值可以恢复到处理器内核的寄存器。允许核心处理器不仅在第一次执行失败的指令之前恢复执行，而且允许以预编程的组数减少执行模式运行。如果指令组的预编程数量无错误地执行，则允许处理器内核恢复正常执行。

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