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11. 发明申请

US20080308801A1 STRUCTURE FOR STOCHASTIC INTEGRATED CIRCUIT PERSONALIZATION 失效
标题翻译： STOCHASTIC集成电路个性化结构
公开(公告)号：US20080308801A1
公开(公告)日：2008-12-18
申请号：US12193288
申请日：2008-08-18
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/58
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译：一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机结构纳米孔特征。在无规纳米孔结构化中间层上形成上导电层。上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。

12. 发明授权

US07435671B2 Trilayer resist scheme for gate etching applications 失效
标题翻译：栅极蚀刻应用的三层抗蚀剂方案
公开(公告)号：US07435671B2
公开(公告)日：2008-10-14
申请号：US11506227
申请日：2006-08-18
申请人： Nicholas C. Fuller , Timothy J. Dalton , Ying Zhang
发明人： Nicholas C. Fuller , Timothy J. Dalton , Ying Zhang
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/28123
摘要： A trilayer resist (TLR) patterning scheme is provided to enable gate conductors, particularly polySi gate conductors, with critical dimensions (CDs) of less than 40 nm and minimal LER and LWR. In accordance with the present invention, the inventive patterning scheme utilizes an organic/inorganic/organic multilayer stack instead of an organic layer used in the prior art. The top organic layer of the inventive TLR is a photoresist material such as a 193 nm photoresist that is located atop an antireflective coating (ARC), which is also comprised of an organic material. The middle inorganic layer of the TLR comprises any oxide layer such as, for example, a low temperature (less than or equal to 250° C.) chemical vapor deposited (CVD) oxide, an oxide derived from TEOS (tetraethylorthosilicate), silicon oxide, a silane oxide, or a Si-containing ARC material. The bottom organic layer of the TLR comprises any organic layer such as, for example, a Near Frictionless Carbon (NFC), a diamond-like carbon, a thermosetting polyarylene ether.
摘要翻译：提供三层抗蚀剂（TLR）图案化方案，以使栅极导体，特别是多晶硅栅极导体，临界尺寸（CD）小于40nm，最小LER和LWR。根据本发明，本发明的图案化方案利用有机/无机/有机多层堆叠代替现有技术中使用的有机层。本发明TLR的顶部有机层是诸如193nm光致抗蚀剂的光致抗蚀剂材料，其位于抗反射涂层（ARC）的顶部，抗反射涂层也由有机材料构成。 TLR的中间无机层包括任何氧化物层，例如化学气相沉积（CVD）的低温（小于或等于250℃），源自TEOS（原硅酸四乙酯），氧化硅，硅烷氧化物或含Si的ARC材料。 TLR的底部有机层包括任何有机层，例如近无摩擦碳（NFC），类金刚石碳，热固性聚亚芳基醚。

13. 发明申请

US20080243972A1 HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS AND METHOD OF FORMING THE SAME 有权
标题翻译：高密度平面磁畴壁记忆装置及其形成方法
公开(公告)号：US20080243972A1
公开(公告)日：2008-10-02
申请号：US11694183
申请日：2007-03-30
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： G06F15/02
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
摘要翻译：具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。

14. 发明申请

US20080160752A1 METHOD FOR CHIP TO PACKAGE INTERCONNECT 审中-公开
标题翻译：芯片封装互连的方法
公开(公告)号：US20080160752A1
公开(公告)日：2008-07-03
申请号：US11619384
申请日：2007-01-03
申请人： Lawrence Clevenger , Timothy J. Dalton , Mukta Ghate Farooq , William Francis Landers , Carl Radens , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy J. Dalton , Mukta Ghate Farooq , William Francis Landers , Carl Radens , Chih-Chao Yang
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/11428 , H01L2224/1145 , H01L2224/1147 , H01L2224/11616 , H01L2224/1184 , H01L2224/11901 , H01L2224/13007 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04953 , H01L2924/0103 , H01L2224/05099
摘要： A damascene method of forming a C4 element includes forming a last level metal layer on a substrate, forming a TV ILD layer on the last level metal layer, forming a lithographically patterned UBM adhesion layer including one of Ti, TiW, Cr and Cu, forming a mandrel layer over the UBM adhesion layer, lithographically patterning the mandrel layer to form an aperture, depositing a solder layer by one of sputtering, evaporation, physical vapor deposition, solder wave or injection molding in the aperture, planarizing the solder layer by CMP, removing the mandrel layer, reflowing the solder to ball the solder to form a ball interconnect, and joining a second substrate with an I/O pad to the ball interconnect.
摘要翻译：形成C4元件的镶嵌方法包括在基底上形成最后一层金属层，在最后一层金属层上形成TV ILD层，形成包括Ti，TiW，Cr和Cu之一的光刻图案的UBM粘附层，形成在UBM粘合层上方的心轴层，光刻图案化心轴层以形成孔，通过溅射，蒸发，物理气相沉积，焊波或注射成型在孔中沉积焊料层，通过CMP平坦化焊料层，去除心轴层，回流焊料以焊接焊料以形成球互连，并将第二衬底与I / O焊盘接合到球互连。

15. 发明申请

US20080160656A1 ADDRESSABLE HIERARCHICAL METAL WIRE TEST METHODOLOGY 失效
标题翻译：可寻址分层金属线测试方法
公开(公告)号：US20080160656A1
公开(公告)日：2008-07-03
申请号：US11619307
申请日：2007-01-03
申请人： Kaushik Chanda , Lawrence Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Chih-Chao Yang
发明人： Kaushik Chanda , Lawrence Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Chih-Chao Yang
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： G01R31/2858 , H01L22/14 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.
摘要翻译：一种监测和测试电迁移和时间依赖介电击穿的方法包括形成可寻址布线测试阵列，其包括多个或水平布置的金属布线和多个分段垂直布置的探测布线，执行单行连续性/电阻检查以确定所述金属布线的哪一行是打开的，执行完全蛇形连续性/电阻检查，以及确定短缺陷的位置。

16. 发明授权

US07371461B2 Multilayer hardmask scheme for damage-free dual damascene processing of SiCOH dielectrics 有权
公开(公告)号：US07371461B2
公开(公告)日：2008-05-13
申请号：US11034480
申请日：2005-01-13
申请人： Nicholas C. M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
发明人： Nicholas C. M. Fuller , Stephen McConnell Gates , Timothy J. Dalton
IPC分类号： B32B9/04 , B32B27/00 , H01L21/31 , H01L21/312 , H01L21/314
CPC分类号： H01L21/0331 , H01L21/76811 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , Y10T428/12576 , Y10T428/12611 , Y10T428/31667 , H01L2924/00
摘要： Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

17. 发明申请

US20070158717A1 INTEGRATED CIRCUIT COMB CAPACITOR 有权
标题翻译：集成电路组合电容器
公开(公告)号：US20070158717A1
公开(公告)日：2007-07-12
申请号：US11306746
申请日：2006-01-10
申请人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
发明人： Daniel C. Edelstein , Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Sarah L. Lane , Anthony K. Stamper
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L23/5223 , H01L21/76814 , H01L21/76816 , H01L21/76831 , H01L28/87 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.
摘要翻译：本发明涉及具有电容器电极的集成电路梳状电容器，其与在相同金属布线级别和相同间距处形成的其它互连和通孔触点相比，在相邻的电容器电极之间具有增加的电容。本发明实现了一种电容器，其使电容容限最小化并且在寄生电极 - 基板电容耦合中保持对称性，而不会通过使用至多一个附加的非临界光掩模来不利地影响在相同布线级别形成的其它互连和通孔触点。

18. 发明授权

US07105445B2 Interconnect structures with encasing cap and methods of making thereof 失效
标题翻译：具有封盖的互连结构及其制造方法
公开(公告)号：US07105445B2
公开(公告)日：2006-09-12
申请号：US11034890
申请日：2005-01-14
申请人： Kwong-Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carl J. Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
发明人： Kwong-Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carl J. Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
IPC分类号： H01L21/44
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect which includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译：一种制造互连的方法，其包括在介电材料中提供互连结构，使所述电介质材料凹陷，使得所述互连结构的一部分在所述电介质的上表面上方延伸，并且在所述互连结构的所述延伸部分上沉积包封盖。

19. 发明授权

US07049209B1 De-fluorination of wafer surface and related structure 有权
标题翻译：晶圆表面脱氟及相关结构
公开(公告)号：US07049209B1
公开(公告)日：2006-05-23
申请号：US10907463
申请日：2005-04-01
申请人： Timothy J. Dalton , Nicholas C. M. Fuller , Kaushik A. Kumar , Catherine Labelle
发明人： Timothy J. Dalton , Nicholas C. M. Fuller , Kaushik A. Kumar , Catherine Labelle
IPC分类号： H01L21/322
CPC分类号： H01L21/31138 , H01L21/02063 , H01L21/3105 , H01L21/76814
摘要： Methods of de-fluorinating a wafer surface after damascene processing and prior to photoresist removal are disclosed, as is a related structure. In one embodiment, the method places the wafer surface in a chamber and exposes the wafer surface to a plasma from a source gas including at least one of nitrogen (N2) and/or hydrogen (H2) at a low power density or ion density. The exposing step removes the chemisorbed and physisorbed fluorine residue present on the wafer surface (and chamber), and improves ultra low dielectric (ULK) interconnect structure robustness and integrity. The exposing step is operative due to the efficacy of hydrogen and nitrogen radicals at removing fluorine-based species and also due to the presence of a minimal amount of ion energy in the plasma. The low power density nitrogen and/or hydrogen-containing plasma process enables negligible ash/adhesion promoter interaction and reduces integration complexity during dual damascene processing of low-k OSG-based materials.
摘要翻译：公开了在镶嵌处理之后和光致抗蚀剂去除之前脱晶晶片表面的方法，如相关结构。在一个实施例中，该方法将晶片表面放置在室中并将晶片表面暴露于来自包括氮（N 2 H 2）和/或氢（H 2 ）。曝光步骤去除晶片表面（和室）上存在的化学吸附和物理吸附的氟残基，并改善超低介电（ULK）互连结构的鲁棒性和完整性。曝光步骤由于氢和氮自由基在除去氟基物质的作用以及由于在等离子体中存在最少量的离子能量而有效。低功率密度氮和/或含氢等离子体方法使得可以忽略灰分/粘附促进剂相互作用，并降低在低k OSG基材料的双镶嵌加工过程中的集成复杂性。

20. 发明授权

US06720249B1 Protective hardmask for producing interconnect structures 失效
标题翻译：用于生产互连结构的保护硬掩模
公开(公告)号：US06720249B1
公开(公告)日：2004-04-13
申请号：US09550943
申请日：2000-04-17
申请人： Timothy J. Dalton , Christopher V. Jahnes , Joyce C. Liu , Sampath Purushothaman
发明人： Timothy J. Dalton , Christopher V. Jahnes , Joyce C. Liu , Sampath Purushothaman
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76802 , H01L21/76811 , H01L21/76813 , H01L21/76816 , H01L21/76829 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a permanent protective hardmask which protects the dielectric properties of a main dielectric layer having a desirably low dielectric constant in a semiconductor device from undesirable increases in the dielectric constant, undesirable increases in current leakage, and low device yield from surface scratching during subsequent processing steps. The protective hardmask further includes a single layer or dual layer sacrificial hardmask particularly useful when interconnect structures such as via openings and/or lines are formed in the low dielectric material during the course of making the final product. The sacrificial hardmask layers and the permanent hardmask layer may be formed in a single step from a same precursor wherein process conditions are altered to provide films of differing dielectric constants. Most preferably, a dual damascene structure has a tri-layer hardmask comprising silicon carbide BLoK™, PECVD silicon nitride, and PECVD silicon dioxide, respectively, formed over a bulk low dielectric constant interlevel dielectric prior to forming the interconnect structures in the interlevel dielectric.
摘要翻译：本发明提供一种永久性保护性硬掩模，其保护半导体器件中具有期望的低介电常数的主电介质层的介电性能，不需要介电常数的增加，不期望的电流泄漏增加，以及在表面划伤期间的低的器件产量后续处理步骤。保护性硬掩模还包括单层或双层牺牲硬掩模，在制造最终产品的过程中，在低电介质材料中形成诸如通孔开口和/或线之间的互连结构时尤其有用。牺牲硬掩模层和永久硬掩模层可以从相同的前体在单个步骤中形成，其中改变工艺条件以提供不同介电常数的膜。最优选地，双镶嵌结构具有三层硬掩模，其在形成层间的互连结构之前分别形成在体低介电常数层间电介质上的碳化硅BLoK TM，PECVD氮化硅和PECVD二氧化硅电介质。

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