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11. 发明授权

US08375155B2 Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer 失效
标题翻译：在多节点对称多处理计算机中管理并发序列化中断广播命令
公开(公告)号：US08375155B2
公开(公告)日：2013-02-12
申请号：US12821752
申请日：2010-06-23
申请人： Garrett M. Drapala , Christine C. Jones , Pak-Kin Mak , Craig R. Walters
发明人： Garrett M. Drapala , Christine C. Jones , Pak-Kin Mak , Craig R. Walters
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of serialized interrupt broadcast commands; receiving, by the communications adapter, a plurality of interrupt tags for the plurality of serialized interrupt broadcast commands, each interrupt tag including an identification of an interrupt service order for a serialized interrupt broadcast command; assigning, by the communications adapter, to each serialized interrupt broadcast command its interrupt tag; and if an interrupt tag assigned to a serialized interrupt broadcast command has an interrupt service order that matches a value of a current operation tag that identifies the next serialized interrupt broadcast command to be exposed to the one or more processors, exposing, by the communications adapter, the serialized interrupt broadcast command to the one or more processors on the compute node to be serviced.
摘要翻译：在多节点对称多处理计算机中管理并发的串行化中断广播命令，包括由计算节点中的通信适配器接收多个串行化的中断广播命令; 由通信适配器接收多个串行化中断广播命令的多个中断标签，每个中断标签包括用于串行化中断广播命令的中断服务命令的标识; 由通信适配器将每个序列化的中断广播命令分配给其中断标签; 并且如果分配给序列化中断广播命令的中断标签具有与当前操作标签的值相匹配的中断服务订单，该当前操作标签的值标识要暴露给所述一个或多个处理器的下一个串行化中断广播命令，则由通信适配器将序列化的中断广播命令发送到要被服务的计算节点上的一个或多个处理器。

12. 发明申请

US20110320737A1 Main Memory Operations In A Symmetric Multiprocessing Computer 有权
标题翻译：对称多处理计算机中的主内存操作
公开(公告)号：US20110320737A1
公开(公告)日：2011-12-29
申请号：US12821540
申请日：2010-06-23
申请人： Garrett M. Drapala , Pak-Kin Mak , Arthur J. O'Neill, JR. , Craig R. Walters
发明人： Garrett M. Drapala , Pak-Kin Mak , Arthur J. O'Neill, JR. , Craig R. Walters
IPC分类号： G06F12/08 , G06F12/14 , G06F12/00
CPC分类号： G06F12/0828 , G06F12/0831
摘要： Main memory operation in a symmetric multiprocessing computer, the computer comprising one or more processors operatively coupled through a cache controller to at least one cache of main memory, the main memory shared among the processors, the computer further comprising input/output (‘I/O’) resources, including receiving, in the cache controller from an issuing resource, a memory instruction for a memory address, the memory instruction requiring writing data to main memory; locking by the cache controller the memory address against further memory operations for the memory address; advising the issuing resource of completion of the memory instruction before the memory instruction completes in main memory; issuing by the cache controller the memory instruction to main memory; and unlocking the memory address only after completion of the memory instruction in main memory.
摘要翻译：在对称多处理计算机中的主存储器操作，所述计算机包括通过高速缓存控制器操作地耦合到主存储器的至少一个高速缓存的一个或多个处理器，所述主存储器在所述处理器之间共享，所述计算机还包括输入/输出（“I / O'）资源，包括在缓存控制器中从发布资源接收存储器地址的存储器指令，需要向主存储器写入数据的存储器指令; 由缓存控制器锁定存储器地址，以防止存储器地址的进一步存储器操作; 在存储器指令在主存储器中完成之前建议完成存储器指令的发布资源; 由缓存控制器发出存储器指令给主存储器; 并且仅在主存储器中的存储器指令完成之后解锁存储器地址。

13. 发明授权

US09558119B2 Main memory operations in a symmetric multiprocessing computer 有权
标题翻译：对称多处理计算机中的主存储器操作
公开(公告)号：US09558119B2
公开(公告)日：2017-01-31
申请号：US12821540
申请日：2010-06-23
申请人： Garrett M. Drapala , Pak-Kin Mak , Arthur J. O'Neill, Jr. , Craig R. Walters
发明人： Garrett M. Drapala , Pak-Kin Mak , Arthur J. O'Neill, Jr. , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0831
摘要： Main memory operation in a symmetric multiprocessing computer, the computer comprising one or more processors operatively coupled through a cache controller to at least one cache of main memory, the main memory shared among the processors, the computer further comprising input/output (‘I/O’) resources, including receiving, in the cache controller from an issuing resource, a memory instruction for a memory address, the memory instruction requiring writing data to main memory; locking by the cache controller the memory address against further memory operations for the memory address; advising the issuing resource of completion of the memory instruction before the memory instruction completes in main memory; issuing by the cache controller the memory instruction to main memory; and unlocking the memory address only after completion of the memory instruction in main memory.
摘要翻译：在对称多处理计算机中的主存储器操作，所述计算机包括通过高速缓存控制器操作地耦合到主存储器的至少一个高速缓存的一个或多个处理器，所述主存储器在所述处理器之间共享，所述计算机还包括输入/输出（“I / O'）资源，包括从发行资源在高速缓存控制器中接收存储器地址的存储器指令，需要向主存储器写入数据的存储器指令; 由缓存控制器锁定存储器地址，以防止存储器地址的进一步存储器操作; 在存储器指令在主存储器中完成之前建议完成存储器指令的发布资源; 由缓存控制器发出存储器指令给主存储器; 并且仅在主存储器中的存储器指令完成之后解锁存储器地址。

14. 发明授权

US08560776B2 Method for expediting return of line exclusivity to a given processor in a symmetric multiprocessing data processing system 失效
标题翻译：在对称多处理数据处理系统中加速线路排他性返回到给定处理器的方法
公开(公告)号：US08560776B2
公开(公告)日：2013-10-15
申请号：US12021403
申请日：2008-01-29
申请人： Garrett M. Drapala , Pak-kin Mak , Vesselina K. Papazova , Craig R. Walters
发明人： Garrett M. Drapala , Pak-kin Mak , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A method and apparatus for eliminating, in a multi-nodes data handling system, contention for exclusivity of lines in cache memory through improved management of system buses, processor cross-invalidate stacks, and the system operations that can lead to these requested cache operations being rejected.
摘要翻译：一种用于在多节点数据处理系统中消除通过改进的系统总线管理，处理器交叉无效堆栈以及可导致这些所请求的高速缓存操作的系统操作的高速缓冲存储器中线路排他性的争用的方法和装置拒绝。

15. 发明申请

US20090083491A1 Storage System and Associated Methods 失效
标题翻译：存储系统及相关方法
公开(公告)号：US20090083491A1
公开(公告)日：2009-03-26
申请号：US11861765
申请日：2007-09-26
申请人： Derrin M. Berger , Michael A. Blake , Garrett M. Drapala , Pak-kin Mak
发明人： Derrin M. Berger , Michael A. Blake , Garrett M. Drapala , Pak-kin Mak
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0851 , G06F12/0855
摘要： A storage system may include storage, a main pipeline to carry data for the storage, and a store pipeline to carry data for the storage. The storage system may also include a controller to prioritize data storage requests for the storage based upon available interleaves and which pipeline is associated with the data storage requests.
摘要翻译：存储系统可以包括存储器，用于存储用于存储数据的主流水线以及用于存储数据的存储流水线。存储系统还可以包括控制器，用于基于可用的交织以及哪个流水线与数据存储请求相关联地对存储的数据存储请求进行优先级排序。

16. 发明申请

US20110320778A1 CENTRALIZED SERIALIZATION OF REQUESTS IN A MULTIPROCESSOR SYSTEM 失效
标题翻译：多处理器系统中的要求的集中串行化
公开(公告)号：US20110320778A1
公开(公告)日：2011-12-29
申请号：US12821933
申请日：2010-06-23
申请人： Garrett M. Drapala , Michael A. Blake , Timothy C. Bronson , Lawrence D. Curley
发明人： Garrett M. Drapala , Michael A. Blake , Timothy C. Bronson , Lawrence D. Curley
IPC分类号： G06F9/30
CPC分类号： G06F9/526 , G06F2209/522
摘要： Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.
摘要翻译：在多处理器系统中串行化指令包括在多处理器系统的中心点处接收多个处理器请求。多个处理器请求中的每一个包括具有请求者需求切换和资源需要切换的需求寄存器。该方法还包括建立指示在中心点存在多个处理器请求的尾部开关，建立多个处理器请求的顺序，以及按照顺序在中心点处理多个处理器请求。

17. 发明授权

US08688880B2 Centralized serialization of requests in a multiprocessor system 失效
标题翻译：在多处理器系统中集中序列化请求
公开(公告)号：US08688880B2
公开(公告)日：2014-04-01
申请号：US12821933
申请日：2010-06-23
申请人： Garrett M. Drapala , Michael A. Blake , Timothy C. Bronson , Lawrence D. Curley
发明人： Garrett M. Drapala , Michael A. Blake , Timothy C. Bronson , Lawrence D. Curley
IPC分类号： G06F12/00 , G06F13/14 , G06F13/38
CPC分类号： G06F9/526 , G06F2209/522
摘要： Serializing instructions in a multiprocessor system includes receiving a plurality of processor requests at a central point in the multiprocessor system. Each of the plurality of processor requests includes a needs register having a requestor needs switch and a resource needs switch. The method also includes establishing a tail switch indicating the presence of the plurality of processor requests at the central point, establishing a sequential order of the plurality of processor requests, and processing the plurality of processor requests at the central point in the sequential order.
摘要翻译：在多处理器系统中串行化指令包括在多处理器系统的中心点处接收多个处理器请求。多个处理器请求中的每一个包括具有请求者需求切换和资源需要切换的需求寄存器。该方法还包括建立指示在中心点存在多个处理器请求的尾部开关，建立多个处理器请求的顺序，以及按照顺序在中心点处理多个处理器请求。

18. 发明授权

US08364904B2 Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computer 失效
标题翻译：多计算节点，对称多处理计算机中的水平缓存持久性
公开(公告)号：US08364904B2
公开(公告)日：2013-01-29
申请号：US12819348
申请日：2010-06-21
申请人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski , Craig R. Walters
发明人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski , Craig R. Walters
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/084
摘要： Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.
摘要翻译：包括在多计算节点SMP计算机中的水平缓存持续性，包括响应于在计算节点的第一个计算节点上驱逐高速缓存行的确定，由第一计算节点广播高速缓存行的逐出通知; 发送接收计算节点的高速缓存行的状态，包括如果高速缓存线从计算节点丢失，则指示该计算节点是否具有可用于高速缓存行的高速缓存存储空间; 由所述第一计算节点根据所述高速缓存行的状态和可用空间来确定所述第一计算节点是否可以驱逐所述高速缓存行而不将高速缓存行写入主存储器; 并且根据所有计算节点中的高速缓存行的一个或多个状态，由每个计算节点更新每个计算节点中的高速缓存行的状态。

19. 发明申请

US20110314227A1 Horizontal Cache Persistence In A Multi-Compute Node, Symmetric Multiprocessing Computer 失效
标题翻译：多计算节点中的水平缓存持久性，对称多处理计算机
公开(公告)号：US20110314227A1
公开(公告)日：2011-12-22
申请号：US12819348
申请日：2010-06-21
申请人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski, JR. , Craig R. Walters
发明人： Michael A. Blake , Lawrence D. Curley , Garrett M. Drapala , Edward J. Kaminski, JR. , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/127 , G06F12/084
摘要： Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.
摘要翻译：包括在多计算节点SMP计算机中的水平缓存持续性，包括响应于在计算节点的第一个计算节点上驱逐高速缓存行的确定，由第一计算节点广播高速缓存行的逐出通知; 发送接收计算节点的高速缓存行的状态，包括如果高速缓存线从计算节点丢失，则指示该计算节点是否具有可用于高速缓存行的高速缓存存储空间; 由所述第一计算节点根据所述高速缓存行的状态和可用空间来确定所述第一计算节点是否可以驱逐所述高速缓存行而不将高速缓存行写入主存储器; 并且根据所有计算节点中的高速缓存行的一个或多个状态，由每个计算节点更新每个计算节点中的高速缓存行的状态。

20. 发明授权

US08458405B2 Cache bank modeling with variable access and busy times 失效
标题翻译：缓存库建模与可变访问和繁忙时间
公开(公告)号：US08458405B2
公开(公告)日：2013-06-04
申请号：US12821891
申请日：2010-06-23
申请人： Timothy C. Bronson , Garrett M. Drapala , Hieu T. Huynh , Kenneth D. Klapproth
发明人： Timothy C. Bronson , Garrett M. Drapala , Hieu T. Huynh , Kenneth D. Klapproth
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0895
摘要： Various embodiments of the present invention manage access to a cache memory. In one embodiment, a set of cache bank availability vectors are generated based on a current set of cache access requests currently operating on a set of cache banks and at least a variable busy time of a cache memory includes the set of cache banks. The set of cache bank availability vectors indicate an availability of the set of cache banks. A set of cache access requests for accessing a set of given cache banks within the set of cache banks is received. At least one cache access request in the set of cache access requests is selected to access a given cache bank based on the a cache bank availability vectors associated with the given cache bank and the set of access request parameters associated with the at least one cache access that has been selected.
摘要翻译：本发明的各种实施例管理对高速缓冲存储器的访问。在一个实施例中，基于当前在一组高速缓存组上操作的当前高速缓存访问请求集合来生成一组高速缓存存储库可用性向量，并且至少高速缓冲存储器的可变繁忙时间包括该组缓存存储体。该组缓存库可用性向量指示该组缓存存储体的可用性。接收用于访问该组缓存组内的一组给定高速缓存存储体的一组缓存访问请求。选择该组高速缓存访问请求中的至少一个高速缓存访问请求以基于与给定高速缓存组相关联的高速缓存存储体可用性向量和与该至少一个高速缓存访问相关联的一组访问请求参数访问给定高速缓存组已被选中。

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