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11. 发明授权

US5805475A Load-store unit and method of loading and storing single-precision floating-point registers in a double-precision architecture 失效
标题翻译：在双精度架构中加载和存储单精度浮点寄存器的加载存储单元和方法
公开(公告)号：US5805475A
公开(公告)日：1998-09-08
申请号：US816067
申请日：1997-03-11
申请人： Michael Putrino , Lee E. Eisen
发明人： Michael Putrino , Lee E. Eisen
IPC分类号： G06F7/57 , G06F9/30 , G06F9/302 , G06F9/312 , G06F7/00 , G06F7/38
CPC分类号： G06F9/30043 , G06F7/483 , G06F9/30014 , G06F9/30025 , G06F2207/382 , G06F7/49905
摘要： A floating point numbers load-store unit includes a translator for converting between the single-precision and double-precision representations, and Special-Case logic for providing Special-Case signals when a store is being performed on zero, infinity, or NaN. A store-float-double instruction is executed by concatenating a suffix to the mantissa in the single-precision floating-point register and replacing the high-order bit of the exponent with a prefix selected as a function of the high-order bit, wherein the resulting mantissa and exponent form a double-precision floating-point number that is then stored to memory. A load-float-double instruction is executed by dropping the suffix from the mantissa of the double-precision floating-point number in memory, and replacing the prefix with the high-order bit, wherein the resulting mantissa and exponent form a single-precision floating-point number that is then loaded into the single-precision floating-point register.
摘要翻译：浮点数加载存储单元包括用于在单精度和双精度表示之间进行转换的转换器，以及当在零，无穷大或NaN上执行存储时提供特殊情况信号的特殊情况逻辑。通过将后缀连接到单精度浮点寄存器中的尾数来执行store-float-double指令，并且以由高位位选择的前缀替换指数的高位，其中所得到的尾数和指数形成双精度浮点数，然后将其存储到存储器中。通过从存储器中的双精度浮点数的尾数丢弃后缀，并用高位替换前缀，执行load-float-double指令，其中所得到的尾数和指数形成单精度浮点数然后加载到单精度浮点寄存器中。

12. 发明授权

US5754811A Instruction dispatch queue for improved instruction cache to queue timing 失效
标题翻译：指令调度队列，用于改进指令缓存到队列时序
公开(公告)号：US5754811A
公开(公告)日：1998-05-19
申请号：US730606
申请日：1996-10-08
申请人： Michael Putrino , Soummya Mallick , Albert John Loper
发明人： Michael Putrino , Soummya Mallick , Albert John Loper
IPC分类号： G06F5/10 , G06F9/38 , G06F9/00
CPC分类号： G06F5/10 , G06F9/3802 , G06F9/3814
摘要： A circular dispatch queue is used to implement an instruction queue, in a microprocessor, in order to reduce the delay associated with the critical timing path between an instruction cache memory and the instruction queue. In the circular dispatch queue, instructions are never moved from one stage to another. Instead, pointers are maintained that indicate the top and bottom instructions within the circular dispatch queue. This technique removes inputs from the multiplexor between the register stages in the circular dispatch queue and the instruction cache memory, thus reducing the critical delay.
摘要翻译：循环调度队列用于在微处理器中实现指令队列，以便减少与指令高速缓冲存储器和指令队列之间的关键定时路径相关联的延迟。在循环调度队列中，指令不会从一个阶段移动到另一个阶段。相反，维护指示循环调度队列中的顶部和底部指令的指针。该技术从循环调度队列中的寄存器阶段和指令高速缓冲存储器之间的多路复用器消除输入，从而减少临界延迟。

13. 发明授权

US4947359A Apparatus and method for prediction of zero arithmetic/logic results 失效
标题翻译：用于预测零运算/逻辑结果的装置和方法
公开(公告)号：US4947359A
公开(公告)日：1990-08-07
申请号：US346147
申请日：1989-05-01
申请人： Stamatis Vassiliadis , Michael Putrino , Ann E. Huffman , Brice J. Feal , Gerald G. Pechanek
发明人： Stamatis Vassiliadis , Michael Putrino , Ann E. Huffman , Brice J. Feal , Gerald G. Pechanek
IPC分类号： G06F7/02 , G06F7/50 , G06F7/57 , G06F9/32
CPC分类号： G06F7/57 , G06F7/026 , G06F7/505 , G06F9/30094 , G06F7/49905
摘要： The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.
摘要翻译：本发明确定何时两个操作数在不使用加法器的情况下直接等效于操作数。在一个实施例中，等于零的和的条件由半数确定以携带和发送从输入操作数导出的运算符。这些操作数用于一些已知类型的加法器，并且因此可以从并行加法器提供给条件预测电路。在另一个实施例中，用于进位保存加法器的等式被修改以提供专门设计用于当操作数之和等于零时确定条件的电路。该和等于零电路大大减少了门延迟和门数，从而允许中央处理单元确定两个操作数的实际总和之前的状态。这样就可以使CPU更快地对条件作出反应，从而提高整体系统的速度。

14. 发明授权

US4924424A Parity prediction for binary adders with selection 失效
标题翻译：具有选择的二进制加法器的奇偶校验预测
公开(公告)号：US4924424A
公开(公告)日：1990-05-08
申请号：US185759
申请日：1988-04-25
申请人： Stamatis Vassiliadis , Eric M. Schwarz , Michael Putrino , Brice J. Feal
发明人： Stamatis Vassiliadis , Eric M. Schwarz , Michael Putrino , Brice J. Feal
IPC分类号： G06F7/00 , G06F7/38 , G06F7/50 , G06F7/508 , G06F11/10
CPC分类号： G06F11/10 , G06F7/00
摘要： An apparatus for predicting parity of a result produced by selection of the most or least significant thirty-two bits produced by a thirty-four bit adder, the parity being predicted concurrently with and independently of the result. Parity for byte Si of the selected result is derived by circuitry implementing the relationship:Pi=yP(m,n-1) V P(n,m+7) V y'P(m+8, n+7)in which Pi is the parity bit for Si, y is the positive sense of a signal indicating selection, of the most significant thirty-two result bits, y' is the complement of y and indicates selection of the least significant thirty-two result bits, P(M,n-1) is parity over the two most significant result bits in the portion of the result covering result bits m through n+7, P(m+8, n+7) is parity of the two least significant bits of the result portion, P(n, m+7) is parity over the central bits of the portion, i is an integer and 0.ltoreq.i.ltoreq.3, m=8i, and n=m+2.

15. 发明授权

US06519620B1 Saturation select apparatus and method therefor 有权
标题翻译：饱和选择装置及其方法
公开(公告)号：US06519620B1
公开(公告)日：2003-02-11
申请号：US09296877
申请日：1999-04-22
申请人： Huy Van Nguyen , Michael Putrino , Charles Philip Roth
发明人： Huy Van Nguyen , Michael Putrino , Charles Philip Roth
IPC分类号： G06F738
CPC分类号： G06F7/49921 , G06F7/50
摘要： A saturation select apparatus and method are implemented. Late stage logic blocks in an adder are provided which combine saturation select control signals with sum generating signals. A first saturation select control is asserted in response to an unsigned saturated instruction, and a second saturation select control is asserted in response to a signed saturated instruction. If either select control is asserted, each logic block outputs a corresponding bit of a respective saturation value. In response to a modulo mode instruction, both select control signals are negated, and each logic block outputs a corresponding bit of the arithmetic operation (sum or difference) implemented by the instruction.
摘要翻译：实现饱和选择装置和方法。提供加法器中的后级逻辑块，其将饱和选择控制信号与和产生信号组合。响应于无符号饱和指令来确定第一饱和选择控制，并且响应于带符号饱和指令断言第二饱和选择控制。如果选择控制被确认，则每个逻辑块输出相应饱和值的相应位。响应于模数模式指令，两个选择控制信号被否定，并且每个逻辑块输出由该指令实现的算术运算（和或差）的相应位。

16. 发明授权

US5809323A Method and apparatus for executing fixed-point instructions within idle execution units of a superscalar processor 失效
标题翻译：用于在超标量处理器的空闲执行单元内执行定点指令的方法和装置
公开(公告)号：US5809323A
公开(公告)日：1998-09-15
申请号：US530552
申请日：1995-09-19
申请人： Lee E. Eisen , Robert T. Golla , Soummya Mallick , Sung-Ho Park , Rajesh B. Patel , Michael Putrino
发明人： Lee E. Eisen , Robert T. Golla , Soummya Mallick , Sung-Ho Park , Rajesh B. Patel , Michael Putrino
IPC分类号： G06F9/302 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/3836 , G06F9/384
摘要： A superscalar processor and method for executing fixed-point instructions within a superscalar processor are disclosed. The superscalar processor has a memory and multiple execution units, including a fixed point execution unit (FXU) and a non-fixed point execution unit (non-FXU). According to the present invention, a set of instructions to be executed are fetched from among a number of instructions stored within memory. A determination is then made if n instructions, the maximum number possible, can be dispatched to the multiple execution units during a first processor cycle if fixed point arithmetic and logical instructions are dispatched only to the FXU. If so, n instructions are dispatched to the multiple execution units for execution. In response to a determination that n instructions cannot be dispatched during the first processor cycle, a determination is made whether a fixed point instruction is available to be dispatched and whether dispatching the fixed point instruction to the non-FXU for execution will result in greater efficiency. In response to a determination that a fixed point instruction is not available to be dispatched or that dispatching the fixed point instruction to the non-FXU will not result in greater efficiency, dispatch of the fixed point instruction is delayed until a second processor cycle. However, in response to a determination that dispatching the fixed point instruction to the non-FXU will result in greater efficiency, the fixed point instruction is dispatched to the non-FXU and executed, thereby improving execution unit utilization.
摘要翻译：公开了一种用于在超标量处理器内执行定点指令的超标量处理器和方法。超标量处理器具有存储器和多个执行单元，包括固定点执行单元（FXU）和非固定点执行单元（非FXU）。根据本发明，从存储在存储器中的多个指令中取出要执行的一组指令。然后如果将固定点算术和逻辑指令仅发送到FXU，则可以在第一处理器周期期间将n个指令（尽可能最大数）分派到多个执行单元进行确定。如果是这样，n个指令被分派到多个执行单元执行。响应于在第一处理器周期期间不能调度n个指令的确定，确定是否可以调度固定点指令，以及是否向非FXU分派定点指令以执行将导致更高的效率。响应于确定不能发送固定点指令或者将定点指令分派到非FXU不会导致更高的效率，所以定点指令的调度被延迟到第二处理器周期。然而，响应于将定点指令发送到非FXU的确定将导致更高的效率，将定点指令分派到非FXU并执行，从而提高执行单元的利用率。

17. 发明授权

US5678016A Processor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serialization 失效
标题翻译：用于管理指令的执行的处理器和方法，所述指令确定在调度指令是否进行序列化之后
公开(公告)号：US5678016A
公开(公告)日：1997-10-14
申请号：US512741
申请日：1995-08-08
申请人： Lee E. Eisen , Robert T. Golla , Christopher H. Olson , Michael Putrino
发明人： Lee E. Eisen , Robert T. Golla , Christopher H. Olson , Michael Putrino
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3836 , G06F9/384
摘要： A method and apparatus are disclosed for managing the execution of a floating-point store instruction within a data processing system including a memory and a superscalar processor having a number of floating-point registers (FPRs). According to the present invention, multiple instructions are dispatched for execution by the processor, including a floating-point store instruction having as an operand the content of a particular FPR. A determination is made whether the particular FPR is a destination register for results of a second instruction which precedes the store instruction in program order. If so, a determination is made whether the second instruction must complete before subsequent instructions can be successfully dispatched. In response to a determination that the second instruction must be completed prior to successfully dispatching subsequent instructions, the floating-point instruction is cancelled and redispatched after the completion of the second instruction. In response to a determination that the second instruction need not be completed prior to successfully dispatching subsequent instructions, execution of the floating-point store instruction is initiated by computing the destination address within memory into which the operand of the floating-point store instruction is to be stored, thereby minimizing the delay in executing a floating-point store instruction.
摘要翻译：公开了一种用于管理包括具有多个浮点寄存器（FPR）的存储器和超标量处理器的数据处理系统内的浮点存储指令的执行的方法和装置。根据本发明，调度多个指令以供处理器执行，包括具有作为特定FPR的内容的操作数的浮点存储指令。确定特定FPR是否是用于以程序顺序在存储指令之前的第二指令的结果的目的地寄存器。如果是，则确定第二条指令是否必须在后续指令可以成功发送之前完成。响应于在成功发送后续指令之前必须完成第二条指令的确定，在完成第二条指令之后，浮点指令被取消并重新分配。响应于在成功发送后续指令之前不需要完成第二指令的确定，通过计算浮点存储指令的操作数所在的存储器内的目标地址来启动浮点存储指令的执行被存储，从而最小化执行浮点存储指令的延迟。

18. 发明授权

US5611063A Method for executing speculative load instructions in high-performance processors 失效
标题翻译：在高性能处理器中执行推测加载指令的方法
公开(公告)号：US5611063A
公开(公告)日：1997-03-11
申请号：US597647
申请日：1996-02-06
申请人： Albert J. Loper , Soummya Mallick , Michael Putrino
发明人： Albert J. Loper , Soummya Mallick , Michael Putrino
IPC分类号： G06F9/312 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30043 , G06F9/383 , G06F9/3842
摘要： A method for selectively executing speculative load instructions in a high-performance processor is disclosed. In accordance with the present disclosure, when a speculative load instruction for which the data is not stored in a data cache is encountered, a bit within an enable speculative load table which is associated with that particular speculative load instruction is read in order to determine a state of the bit. If the associated bit is in a first state, data for the speculative load instruction is requested from a system bus and further execution of the speculative load instruction is then suspended to wait for control signals from a branch processing unit. If the associated bit is in a second state, the execution of the speculative load instruction is immediately suspended to wait for control signals from the branch processing unit. If the speculative load instruction is executed in response to the control signals, then the associated bit in the enable speculative load table will be set to the first state. However, if the speculative load instruction is not executed in response to the control signals, then the associated bit in the enable speculative load table is set to the second state. In this manner, the displacement of useful data in the data cache due to wrongful execution of the speculative load instruction is avoided.
摘要翻译：公开了一种用于选择性地执行高性能处理器中的推测性加载指令的方法。根据本公开，当遇到数据未被存储在数据高速缓冲存储器中的推测性加载指令时，读取与该特定推测加载指令相关联的使能投机载入表中的位，以便确定状态的位。如果关联位处于第一状态，则从系统总线请求用于推测加载指令的数据，然后暂停推测加载指令的进一步执行，以等待来自分支处理单元的控制信号。如果相关联的位处于第二状态，则推测加载指令的执行被立即停止，以等待来自分支处理单元的控制信号。如果响应于控制信号执行推测加载指令，则使能推测加载表中的关联位将被设置为第一状态。然而，如果不响应于控制信号执行推测加载指令，则使能推测负载表中的关联位被设置为第二状态。以这种方式，避免了由于推测加载指令的错误执行而在数据高速缓存中的有用数据的位移。

19. 发明授权

US5375078A Arithmetic unit for performing XY+B operation 失效
标题翻译：用于执行XY + B操作的算术单元
公开(公告)号：US5375078A
公开(公告)日：1994-12-20
申请号：US991052
申请日：1992-12-15
申请人： David A. Hrusecky , Michael Putrino
发明人： David A. Hrusecky , Michael Putrino
IPC分类号： G06F7/544 , G06F7/38
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49936 , G06F7/49947
摘要： An arithmetic unit rapidly performs an XY+B floating point operation and yields a result equivalent to truncation of the product of X and Y before adding to B. Standard circuitry produces partial products from multiplier X and multiplicand Y, and a standard adder adds the partial products to yield a sum vector and a carry vector. Meanwhile, other circuitry predicts whether a most significant digit of a sum of the sum vector and the carry vector is zero or nonzero, based on less than all bits of the multiplier X and the multiplicand Y. If the most significant digit is certainly not equal to zero, a multiplexing circuit passes to a second adder a most significant N digits of the sum vector, a most significant N digits of the carry vector, a carry bit resulting from addition an (N-1)th most significant digit and lesser significant digits of the sum vector with an (N+1)th most significant digit and less significant digits of the carry vector, and an operand B. If the most significant digit is certainly equal to zero, then the multiplexing circuitry passes to the second adder a most significant N+1 digits of the sum vector, a most significant N+1 digits of the carry vector, a carry bit resulting from the addition of an (N+2)th most significant digit and less significant digits of the sum vector with an (N+2)th most significant digit and lesser significant digits of the carry vector, and the operand B.
摘要翻译：算术单元快速执行XY + B浮点运算，并产生等于X和Y乘积截断的结果，然后再加上B。标准电路产生乘法器X和被乘数Y的部分乘积，标准加法器将部分产生一个和矢量和一个进位向量。同时，其他电路基于小于乘法器X和乘法器Y的所有比特来预测和矢量和进位向量之和的最高有效位是零还是非零。如果最高有效位肯定不相等为零，多路复用电路将和向量的最高有效N位传送给第二加法器，进位向量的最高有效N位，由相加第（N-1）个最高有效数字和较小有效位产生的进位位具有第（N + 1）个最高有效位和进位向量的低有效位的和矢量的位数以及操作数B.如果最高有效位肯定等于零，则多路复用电路传递到第二加法器和矢量的最高有效N + 1个数字，进位向量的最高有效N + 1个数字，由相加和矢量的第（N + 2）个最高有效位和较低有效位相加而产生的进位位最多（N + 2）进位向量的有效数字和较低有效数字，以及操作数B.

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