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11. 发明申请

US20080171428A1 Methods of Forming Spacer Patterns Using Assist Layer For High Density Semiconductor Devices 有权
标题翻译：使用高密度半导体器件辅助层形成间隔图的方法
公开(公告)号：US20080171428A1
公开(公告)日：2008-07-17
申请号：US11623314
申请日：2007-01-15
申请人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
发明人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , H01L21/0337 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

12. 发明申请

US20100240182A1 Spacer Patterns Using Assist Layer For High Density Semiconductor Devices 有权
标题翻译：使用高密度半导体器件辅助层的间隔图
公开(公告)号：US20100240182A1
公开(公告)日：2010-09-23
申请号：US12791103
申请日：2010-06-01
申请人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
发明人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小光刻可分辨元件尺寸。形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

13. 发明授权

US07773403B2 Spacer patterns using assist layer for high density semiconductor devices 有权
标题翻译：使用辅助层的高密度半导体器件的间隔图案
公开(公告)号：US07773403B2
公开(公告)日：2010-08-10
申请号：US11623315
申请日：2007-01-15
申请人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
发明人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
IPC分类号： G11C5/06
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻解析的元件尺寸。形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

14. 发明授权

US07592225B2 Methods of forming spacer patterns using assist layer for high density semiconductor devices 有权
标题翻译：使用辅助层形成间隔图案的方法用于高密度半导体器件
公开(公告)号：US07592225B2
公开(公告)日：2009-09-22
申请号：US11623314
申请日：2007-01-15
申请人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
发明人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/32139 , H01L21/0337 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

15. 发明申请

US20080169567A1 Spacer Patterns Using Assist Layer for High Density Semiconductor Devices 有权
标题翻译：使用辅助层进行高密度半导体器件的间隔图
公开(公告)号：US20080169567A1
公开(公告)日：2008-07-17
申请号：US11623315
申请日：2007-01-15
申请人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
发明人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
IPC分类号： H01L23/52
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

16. 发明授权

US07960266B2 Spacer patterns using assist layer for high density semiconductor devices 有权
标题翻译：使用辅助层的高密度半导体器件的间隔图案
公开(公告)号：US07960266B2
公开(公告)日：2011-06-14
申请号：US12791103
申请日：2010-06-01
申请人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
发明人： James Kai , George Matamis , Tuan Duc Pham , Masaaki Higashitani , Takashi Orimoto
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

17. 发明授权

US07915664B2 Non-volatile memory with sidewall channels and raised source/drain regions 有权
标题翻译：具有侧壁通道和升高的源极/漏极区域的非易失性存储器
公开(公告)号：US07915664B2
公开(公告)日：2011-03-29
申请号：US12105242
申请日：2008-04-17
申请人： Henry Chien , Takashi Orimoto , George Matamis , James Kai , Vinod R. Purayath
发明人： Henry Chien , Takashi Orimoto , George Matamis , James Kai , Vinod R. Purayath
IPC分类号： H01L29/788
CPC分类号： G11C8/10 , G11C8/04 , G11C11/5621 , G11C16/0483 , G11C19/00 , H01L21/28273 , H01L27/11521
摘要： A non-volatile storage system in which a sidewall insulating layer of a floating gate is significantly thinner than a thickness of a bottom insulating layer, and in which raised source/drain regions are provided. During programming or erasing, tunneling occurs predominantly via the sidewall insulating layer and the raised source/drain regions instead of via the bottom insulating layer. The floating gate may have a uniform width or an inverted T shape. The raised source/drain regions may be epitaxially grown from the substrate, and may include a doped region above an undoped region so that the channel length is effectively extended from beneath the floating gate and up into the undoped regions, so that short channel effects are reduced. The ratio of the thicknesses of the sidewall insulating layer to the bottom insulating layer may be about 0.3 to 0.67.
摘要翻译：一种非易失性存储系统，其中浮动栅极的侧壁绝缘层比底部绝缘层的厚度明显薄，并且其中设置有凸起的源极/漏极区域。在编程或擦除期间，隧道主要通过侧壁绝缘层和凸起的源极/漏极区域而不是通过底部绝缘层发生。浮动门可以具有均匀的宽度或倒T形。凸起的源极/漏极区域可以从衬底外延生长，并且可以包括在未掺杂区域上方的掺杂区域，使得沟道长度从浮置栅极下方有效地延伸并且向上延伸到未掺杂区域，使得短沟道效应为减少侧壁绝缘层与底部绝缘层的厚度的比例可以为约0.3至0.67。

18. 发明授权

US08030160B2 Methods of forming NAND flash memory with fixed charge 有权
标题翻译：用固定电荷形成NAND闪存的方法
公开(公告)号：US08030160B2
公开(公告)日：2011-10-04
申请号：US12729874
申请日：2010-03-23
申请人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
发明人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.
摘要翻译：一串串联的非易失性存储单元包括位于浮置栅极和下面的衬底表面之间的固定电荷。这样的固定电荷会影响衬底的下层部分中电荷载流子的分布，从而影响器件的阈值电压。固定电荷层也可以在源极/漏极区域上延伸。

19. 发明申请

US20100178742A1 METHODS OF FORMING NAND FLASH MEMORY WITH FIXED CHARGE 有权
标题翻译：形成具有固定电荷的NAND闪存存储器的方法
公开(公告)号：US20100178742A1
公开(公告)日：2010-07-15
申请号：US12729874
申请日：2010-03-23
申请人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
发明人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.
摘要翻译：一串串联的非易失性存储单元包括位于浮置栅极和下面的衬底表面之间的固定电荷。这样的固定电荷会影响衬底的下层部分中电荷载流子的分布，从而影响器件的阈值电压。固定电荷层也可以在源极/漏极区域上延伸。

20. 发明授权

US07619926B2 NAND flash memory with fixed charge 有权
标题翻译： NAND闪存固定充电
公开(公告)号：US07619926B2
公开(公告)日：2009-11-17
申请号：US11692958
申请日：2007-03-29
申请人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
发明人： Takashi Orimoto , George Matamis , Henry Chien , James Kai
IPC分类号： G11C11/34
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42324 , H01L29/7881
摘要： A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also.
摘要翻译：一串串联的非易失性存储单元包括位于浮置栅极和下面的衬底表面之间的固定电荷。这样的固定电荷会影响衬底的下层部分中电荷载流子的分布，从而影响器件的阈值电压。固定电荷层也可以在源极/漏极区域上延伸。

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