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11. 发明授权

US4625180A Intermittently operated frequency synthesizer having suppressed frequency instability 失效
标题翻译：具有抑制频率不稳定性的间歇操作频率合成器
公开(公告)号：US4625180A
公开(公告)日：1986-11-25
申请号：US813139
申请日：1985-12-24
申请人： Eiji Itaya , Takeshi Takano , Takaharu Nakamura
发明人： Eiji Itaya , Takeshi Takano , Takaharu Nakamura
IPC分类号： H03L7/18 , H03L7/08 , H03L7/081 , H03L7/087 , H03L7/199
CPC分类号： H03L7/081 , H03L7/0802 , H03L7/087 , H03L7/199
摘要： A frequency synthesizer having an intermittently operated PLL circuit in which power is intermittently applied to a prescaler to reduce power consumption. The PLL circuit is operated such that fluctuations in the frequency synthesizer output frequency do not occur. This stability in the output frequency results from selectively providing signals to the phase comparator within the PLL circuit only during a time period beginning after power is applied to the prescaler and ending before power is removed from the prescaler.
摘要翻译：一种具有间歇操作的PLL电路的频率合成器，其中间歇地施加电力给预分频器以降低功耗。操作PLL电路使得不会发生频率合成器输出频率的波动。输出频率的这种稳定性是由于只有在向预分频器施加电源并在从预分频器断电之前结束的时间段内，才可以选择性地向PLL电路内的相位比较器提供信号。

12. 发明授权

US4394626A Phase synchronizing circuit 失效
标题翻译：相位同步电路
公开(公告)号：US4394626A
公开(公告)日：1983-07-19
申请号：US211847
申请日：1980-12-01
申请人： Hiroshi Kurihara , Sadao Takenaka , Eiji Itaya
发明人： Hiroshi Kurihara , Sadao Takenaka , Eiji Itaya
IPC分类号： H03L7/10 , H03L7/087 , H04L7/027 , H04L27/00 , H04L27/227 , H03L7/08
CPC分类号： H04L27/2273 , H03L7/087 , H04L7/027 , H04L2027/003 , H04L2027/0057
摘要： A phase synchronizing circuit, wherein two phase detectors are used in quadrature to detect the phase of an input signal and to avoid hang-up when the phase of the input signal changes abruptly by 180.degree.. The two detected phase signals are then multiplied by a locally generated reference signal and re-combined, so that a synchronized output signal having reduced phase jitter results. This circuit is also incorporated in an N-phase PSK system, where it is used as a synchronizer and not as a demodulator. In a receiver for such a PSK system, the frequency of the received signal is multiplied by N, the phase synchronizer circuit of the invention is then used to extract the carrier (at a N times higher frequency), and a divider is then used to convert the synchronized carrier provided by the synchronizer circuit of the invention down to the original frequency.
摘要翻译：相位同步电路，其中两相检测器用于正交检测输入信号的相位，并且当输入信号的相位突然变化180°时避免挂起。然后将两个检测到的相位信号乘以本地产生的参考信号并重新组合，使得具有降低的相位抖动的同步输出信号结果。该电路也被并入N相PSK系统中，其被用作同步器而不是解调器。在这种PSK系统的接收机中，将接收信号的频率乘以N，然后使用本发明的相位同步器电路提取载波（频率为N倍），然后使用分频器将由本发明的同步器电路提供的同步载波转换为原始频率。

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