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11. 发明授权

US5450365A Memory card control device 失效
标题翻译：存储卡控制装置
公开(公告)号：US5450365A
公开(公告)日：1995-09-12
申请号：US243790
申请日：1994-05-17
申请人： Kaoru Adachi
发明人： Kaoru Adachi
IPC分类号： G06F1/26 , G06F3/00 , G06F12/00 , G11C5/14 , G11C7/00 , G06K7/06
CPC分类号： G11C5/14
摘要： In a memory card control device for interfacing an electronic still camera or similar electronic equipment and a memory card removably mounted on the equipment, a data processing device operates only at a supply voltage of 5 volts while a logic circuit operates at a supply voltage of 3 volts. A first level shifter converts the level of signals output from the memory card to a level matching the logic circuit. A second level shifter converts the level of signals output from the logic circuit to 5 volts and transfers it to the processing device, while converting the level of signals output from the processing device to 3 volts and feeding it to the logic circuit. The control device accommodates various kinds of memory cards each having a particular rated supply voltage.
摘要翻译：在用于连接电子静态照相机或类似电子设备的存储卡控制装置和可移除地安装在设备上的存储卡之间，数据处理装置仅在5伏的电源电压下工作，而逻辑电路以3的电源电压工作伏。第一电平移位器将从存储卡输出的信号电平转换为与逻辑电路相匹配的电平。第二电平移位器将从逻辑电路输出的信号电平转换为5伏，并将其传送到处理装置，同时将从处理装置输出的信号电平转换为3伏并将其馈送到逻辑电路。控制装置容纳各种具有特定额定电源电压的存储卡。

12. 发明授权

US5442643A Integrated circuit chip with testing circuits and method of testing the same 失效
标题翻译：具有测试电路的集成电路芯片和测试方法相同
公开(公告)号：US5442643A
公开(公告)日：1995-08-15
申请号：US035595
申请日：1993-03-23
申请人： Kaoru Adachi
发明人： Kaoru Adachi
IPC分类号： G01R31/28 , G06F11/273 , H01L21/66
CPC分类号： G06F11/2733
摘要： An integrated circuit (IC) chip which can be tested even after being packaged on a circuit board together with other IC chips, and a method of testing such IC chips on the circuit board are provided. The IC chip has a main IC section to which a particular function is assigned, and a plurality of testing circuits capable of freely extracting output data of the main IC section on a common bus. An interface is also provided on the IC chip which receives signals for controlling the testing circuits from the outside. The testing circuits, therefore, can selectively hold data sent from the outside or data from the main IC section and then send the data out via input/output terminals thereof or the interface.
摘要翻译：提供了即使在与其他IC芯片一起封装在电路板上也可以测试的集成电路（IC）芯片，以及在电路板上测试这种IC芯片的方法。 IC芯片具有分配特定功能的主IC部分和能够在公共总线上自由提取主IC部分的输出数据的多个测试电路。在IC芯片上还设置有从外部接收用于控制测试电路的信号的接口。因此，测试电路可以选择性地保持从外部发送的数据或来自主IC部分的数据，然后通过其输入/输出端或接口发送数据。

13. 外观设计

USD681070S1 Power shovel 有权
公开(公告)号：USD681070S1
公开(公告)日：2013-04-30
申请号：US29431777
申请日：2012-09-11
申请人： Hironori Tsukamoto , Kenji Kawamoto , Shintaro Sakitani , Kaoru Adachi , Hiroshi Kanamaru
设计人： Hironori Tsukamoto , Kenji Kawamoto , Shintaro Sakitani , Kaoru Adachi , Hiroshi Kanamaru

14. 发明授权

US06959357B2 Integrated circuit and method of controlling same 失效
标题翻译：集成电路及其控制方法
公开(公告)号：US06959357B2
公开(公告)日：2005-10-25
申请号：US09852683
申请日：2001-05-11
申请人： Kaoru Adachi
发明人： Kaoru Adachi
IPC分类号： G06F3/00 , G06F13/36 , G06F13/40 , G06F13/00 , G06F1/06
CPC分类号： G06F13/4022
摘要： Bus-connected circuits are made to operate stably and at high speed. A cache memory for high-speed access and a DRAM for low-speed access are connected to a CPU by an address bus, control bus and data transfer bus. A switch is provided in the bus at a point between the cache memory and DRAM and the switch is opened at the time of high-speed access. Since bus length is essentially shortened at such time, the cache memory can be accessed stably at high speed. When the DRAM is accessed, the switch is closed.
摘要翻译：总线连接电路可以稳定和高速运行。用于高速存取的高速缓冲存储器和用于低速存取的DRAM通过地址总线，控制总线和数据传输总线连接到CPU。在高速缓冲存储器和DRAM之间的点处在总线中提供开关，并且在高速访问时打开开关。由于总线长度在这样的时间基本上被缩短，所以高速缓冲存储器可以被高速稳定地访问。当DRAM被访问时，开关闭合。

15. 发明授权

US06744007B2 Laser welding method 失效
标题翻译：激光焊接方法
公开(公告)号：US06744007B2
公开(公告)日：2004-06-01
申请号：US10050832
申请日：2002-01-18
申请人： Kazuhiko Ono , Kaoru Adachi , Tairou Samejima , Akitoshi Masamura
发明人： Kazuhiko Ono , Kaoru Adachi , Tairou Samejima , Akitoshi Masamura
IPC分类号： B23K2026
CPC分类号： B23K26/24 , B23K26/211
摘要： This invention provides a laser welding method capable of supplying a filler wire to a welding object portion in a stabilized condition so as to stabilize welding quality. More specifically, the filler wire is supplied to the welding object portion while the laser beam is projected to the welding object portion. At this time, the filler wire is supplied obliquely from forward or backward in the welding advance direction such that the angle between the supplying direction and beam axis L of the laser beam is less than 45°.
摘要翻译：本发明提供一种激光焊接方法，其能够在稳定状态下向焊接对象部供给填充焊丝，以稳定焊接质量。更具体地，当激光束投射到焊接对象部分时，将填充焊丝提供给焊接对象部分。此时，在焊接前进方向上，从前后方向倾斜地供给填充线，使得激光束的供给方向与光束轴L之间的角度小于45°。

16. 发明授权

US06084633A Digital electronic still-video camera, and method of controlling same 失效
公开(公告)号：US06084633A
公开(公告)日：2000-07-04
申请号：US991206
申请日：1992-12-15
申请人： Kouichi Gouhara , Kaoru Adachi , Kenji Moronaga
发明人： Kouichi Gouhara , Kaoru Adachi , Kenji Moronaga
IPC分类号： H04N1/41 , H04N1/21 , H04N5/225 , H04N5/232 , H04N5/907 , H04N5/92 , H04N5/926 , H04N5/76
CPC分类号： H04N1/2141 , H04N1/2112 , H04N1/215 , H04N1/2158 , H04N5/907 , H04N5/9261
摘要： A digital electronic still-video camera is capable of performing rapid-sequence photography at high speeds. When a rapid-sequence photographic mode has been set, each of a plurality of frames of image data obtained by such photography is compressed. Image data which forms a single multiple-frame picture is constructed by a set of image data composed of the compressed plurality of frames. Thinning out is performed in order to compress the image data. The image data is successively stored, while being thinned out, at corresponding addresses of an image memory in such a manner that a multiple-frame picture is constructed in the image memory. After photography in the rapid-sequence mode ends, the image data in the image memory is subjected to data compression and then recorded on a memory card.

17. 发明授权

US5361228A IC memory card system having a common data and address bus 失效
标题翻译：具有公共数据和地址总线的IC存储卡系统
公开(公告)号：US5361228A
公开(公告)日：1994-11-01
申请号：US54575
申请日：1993-04-30
申请人： Kaoru Adachi , Katsuya Makioka
发明人： Kaoru Adachi , Katsuya Makioka
IPC分类号： G06K19/073 , G11C5/06 , G11C16/10 , G11C7/00 , G11C8/00
CPC分类号： G11C16/102 , G11C5/066
摘要： An IC memory card system has a host for processing data, and an IC memory card removably connected to the host and incorporating a data recording medium implemented by an electrically erasable programmable semiconductor memory. The host comprises a system controller for sending to the memory card an address/data signal for distinguishing an address and data by a logical bilevel state, a read/write signal for distinguishing reading of data and writing of data in the semiconductor memory by a logical bilevel state, and an erase signal for erasing data stored in the semiconductor memory by a logical bilevel state as control signals, and bus clock pulses each being synchronous to a particular address and particular data. The IC memory card comprises a control circuit responsive to the address/data signal, read/write signal, erase signal and bus clock pulses for distinguishing an address and data, distinguishing reading and writing, and determining whether or not to erase existing data, and then reading or writing data in the semiconductor memory or erasing the existing data.
摘要翻译： IC存储卡系统具有用于处理数据的主机，以及可移除地连接到主机并且并入由电可擦除可编程半导体存储器实现的数据记录介质的IC存储卡。主机包括系统控制器，用于向存储卡发送用于区分地址和数据的逻辑双电平状态的地址/数据信号，用于区分数据读取和半导体存储器中的数据写入的逻辑的读/写信号二级状态，以及擦除信号，用于通过逻辑二级状态擦除存储在半导体存储器中的数据作为控制信号，以及每个与特定地址和特定数据同步的总线时钟脉冲。 IC存储卡包括响应于地址/数据信号，读/写信号，擦除信号和总线时钟脉冲的控制电路，用于区分地址和数据，区分读和写，以及确定是否擦除现有数据，以及然后读取或写入半导体存储器中的数据或擦除现有数据。

18. 外观设计

USD680136S1 Counterweight for construction machine 有权
公开(公告)号：USD680136S1
公开(公告)日：2013-04-16
申请号：US29431776
申请日：2012-09-11
申请人： Hironori Tsukamoto , Kenji Kawamoto , Shintaro Sakitani , Kaoru Adachi , Hiroshi Kanamaru
设计人： Hironori Tsukamoto , Kenji Kawamoto , Shintaro Sakitani , Kaoru Adachi , Hiroshi Kanamaru

19. 外观设计

USD679734S1 Power shovel 有权
公开(公告)号：USD679734S1
公开(公告)日：2013-04-09
申请号：US29431775
申请日：2012-09-11
申请人： Hironori Tsukamoto , Kenji Kawamoto , Shintaro Sakitani , Kaoru Adachi , Hiroshi Kanamaru
设计人： Hironori Tsukamoto , Kenji Kawamoto , Shintaro Sakitani , Kaoru Adachi , Hiroshi Kanamaru

20. 发明授权

US07277586B2 Images combination processing system, images combination processing method, and images combination processing program 失效
标题翻译：图像组合处理系统，图像组合处理方法和图像组合处理程序
公开(公告)号：US07277586B2
公开(公告)日：2007-10-02
申请号：US10755386
申请日：2004-01-13
申请人： Kaoru Adachi
发明人： Kaoru Adachi
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： H04N1/41 , H04N5/335 , H04N19/146 , H04N19/30 , H04N19/423 , H04N19/436 , H04N19/46 , H04N19/60 , H04N19/70
摘要： An images combination processing system has a CCD or an imaging element including CCDs for picking up an image, compression processing portions for applying JPEG compression, etc. to image data in respective areas into which a picked-up image is divided, a buffer for storing temporarily compressed data that were processed by the compression processing portions, a compressed data combining portion for reading the compressed data being processed by respective compression processing portions from the buffer and combining them into one image file, and a storage media. Each compression processing portion has a restart marker inserting portion for inserting restart markers into the compressed data while circulating eight types of restart markers and also inserting a special restart marker into a rearmost portion of the compressed data, and a data length counter for counting a data length of the compressed data to which the restart markers are inserted.
摘要翻译：图像组合处理系统具有CCD或摄像元件，其包括用于拾取图像的CCD，用于应用JPEG压缩的压缩处理部分等，以将被分割的拍摄图像分成各个区域中的图像数据，用于存储的缓冲器由压缩处理部分处理的临时压缩数据，压缩数据组合部分，用于从缓冲器读取由各个压缩处理部分处理的压缩数据，并将它们组合成一个图像文件;以及存储介质。每个压缩处理部分具有重新启动标记插入部分，用于在循环八种类型的重新启动标记的同时循环插入重新启动标记，并且还将特殊重启标记插入到压缩数据的最后部分中，以及用于对数据进行计数的数据长度计数器插入重新启动标记的压缩数据的长度。

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