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11. 发明授权

US07309901B2 Field effect transistors (FETs) with multiple and/or staircase silicide 失效
标题翻译：具有多个和/或阶梯硅化物的场效应晶体管（FET）
公开(公告)号：US07309901B2
公开(公告)日：2007-12-18
申请号：US10908087
申请日：2005-04-27
申请人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
发明人： Xiangdong Chen , Sunfei Fang , Zhijiong Luo , Haining Yang , Huilong Zhu
IPC分类号： H01L21/8232
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.
摘要翻译：一种半导体结构及其形成方法。半导体结构包括场效应晶体管（FET），其具有设置在第一和第二源极/漏极（S / D）延伸区域之间的沟道区域，第一和第二源极/漏极（S / D）延伸区域又分别与第一和第二S / D区域直接物理接触。形成第一和第二硅化物区域，使得第一硅化物区域与第一S / D区域和第一S / D延伸区域直接物理接触，而第二硅化物区域与第二S / D区域直接物理接触区域和第二S / D扩展区域。对于与第一S / D延伸区域接触的区域，第一硅化物区域比与第一S / D区域接触的区域更薄。类似地，对于与第二S / D延伸区域接触的区域，第二硅化物区域比与第二S / D区域接触的区域更薄。

12. 发明申请

US20070249131A1 Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors 有权
标题翻译：用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法
公开(公告)号：US20070249131A1
公开(公告)日：2007-10-25
申请号：US11408522
申请日：2006-04-21
申请人： Scott Allen , Cyril Cabral , Kevin Dezfulian , Sunfei Fang , Brian Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement Wann , Huilong Zhu
发明人： Scott Allen , Cyril Cabral , Kevin Dezfulian , Sunfei Fang , Brian Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement Wann , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

13. 发明申请

US20070105299A1 DUAL STRESS MEMORY TECHNIQUE METHOD AND RELATED STRUCTURE 有权
标题翻译：双应力记忆技术方法及相关结构
公开(公告)号：US20070105299A1
公开(公告)日：2007-05-10
申请号：US11164114
申请日：2005-11-10
申请人： Sunfei Fang , Jun Kim , Zhijiong Luo , Hung Ng , Nivo Rovedo , Young Teh
发明人： Sunfei Fang , Jun Kim , Zhijiong Luo , Hung Ng , Nivo Rovedo , Young Teh
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/823807
摘要： A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.
摘要翻译：公开了一种在包括nFET和PFET以及相关结构的半导体器件中提供双重应力记忆技术的方法。该方法的一个实施例包括在nFET上形成拉伸应力层，并在pFET上形成压应力层，退火以在半导体器件中记忆应力并去除应力层。压应力层可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。退火步骤可以包括使用约400-1200℃的温度。高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET中。

14. 发明授权

US07105440B2 Self-forming metal silicide gate for CMOS devices 失效
标题翻译：用于CMOS器件的自成型金属硅化物栅极
公开(公告)号：US07105440B2
公开(公告)日：2006-09-12
申请号：US10905629
申请日：2005-01-13
申请人： Zhijiong Luo , Sunfei Fang , Huilong Zhu
发明人： Zhijiong Luo , Sunfei Fang , Huilong Zhu
IPC分类号： H01L21/44
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L29/665 , H01L29/7833
摘要： A process for forming a metal suicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (polysilicon or amorphous silicon) is formed overlying the gate dielectric; a layer of metal is then formed on the first layer, and a second layer of silicon on the metal layer. A high-temperature (>700° C.) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer above the gate dielectric by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer from silicon in the second layer. The thicknesses of the layers are such that in the high-temperature processing, substantially all of the first layer and at least a portion of the second layer are replaced by silicide material. Accordingly, a fully silicided gate structure may be produced.
摘要翻译：在FET器件中形成金属硅化物栅极的方法，其中硅化物自成型（即，不需要单独的金属/硅反应步骤形成），并且不需要CMP材料的CMP或回蚀。第一层硅材料（多晶硅或非晶硅）形成在栅极电介质上方; 然后在第一层上形成金属层，在金属层上形成第二层硅。随后进行高温（> 700℃）处理步骤，例如源极/漏极激活退火; 该步骤通过金属与第一层中的硅的反应在栅电介质上形成硅化物层是有效的。可以进行第二高温处理步骤（例如源极/漏极硅化），其有效地从第二层中的硅形成第二硅化物层。层的厚度使得在高温处理中，基本上所有的第一层和第二层的至少一部分被硅化物材料代替。因此，可以产生完全硅化的栅极结构。

15. 发明申请

US20060163569A1 Test structure of semiconductor device 有权
标题翻译：半导体器件的测试结构
公开(公告)号：US20060163569A1
公开(公告)日：2006-07-27
申请号：US11218397
申请日：2005-09-02
申请人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Wee Tan , Sunfei Fang , Zhijiong Luo
发明人： Min-chul Sun , Ja-hum Ku , Brian Greene , Manfred Eller , Wee Tan , Sunfei Fang , Zhijiong Luo
IPC分类号： H01L23/58 , H01L29/10
CPC分类号： H01L22/34
摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.
摘要翻译：提供半导体器件的测试结构。测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域，第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

16. 发明申请

US20060154413A1 SELF-FORMING METAL SILICIDE GATE FOR CMOS DEVICES 失效
标题翻译：用于CMOS器件的自成型金属硅化物栅
公开(公告)号：US20060154413A1
公开(公告)日：2006-07-13
申请号：US10905629
申请日：2005-01-13
申请人： Zhijiong Luo , Sunfei Fang , Huilong Zhu
发明人： Zhijiong Luo , Sunfei Fang , Huilong Zhu
IPC分类号： H01L21/8234
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L29/665 , H01L29/7833
摘要： A process for forming a metal suicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (polysilicon or amorphous silicon) is formed overlying the gate dielectric; a layer of metal is then formed on the first layer, and a second layer of silicon on the metal layer. A high-temperature (>700° C.) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer above the gate dielectric by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer from silicon in the second layer. The thicknesses of the layers are such that in the high-temperature processing, substantially all of the first layer and at least a portion of the second layer are replaced by silicide material. Accordingly, a fully silicided gate structure may be produced.
摘要翻译：在FET器件中形成金属硅化物栅极的方法，其中硅化物自成型（即，不需要单独的金属/硅反应步骤形成），并且不需要CMP材料的CMP或回蚀。第一层硅材料（多晶硅或非晶硅）形成在栅极电介质上方; 然后在第一层上形成金属层，在金属层上形成第二层硅。随后进行高温（> 700℃）处理步骤，例如源极/漏极激活退火; 该步骤通过金属与第一层中的硅的反应在栅电介质上形成硅化物层是有效的。可以进行第二高温处理步骤（例如源极/漏极硅化），其有效地从第二层中的硅形成第二硅化物层。层的厚度使得在高温处理中，基本上所有的第一层和第二层的至少一部分被硅化物材料代替。因此，可以产生完全硅化的栅极结构。

17. 发明申请

US20060121665A1 METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 有权
标题翻译：在CMOS技术中形成自对准双重杀菌剂的方法
公开(公告)号：US20060121665A1
公开(公告)日：2006-06-08
申请号：US11254934
申请日：2005-10-20
申请人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
发明人： Sunfei Fang , Cyril Cabral , Chester Dziobkowski , John Ellis-Monaghan , Christian Lavoie , Zhijiong Luo , James Nakos , An Steegen , Clement Wann
IPC分类号： H01L21/8238 , H01L21/44
CPC分类号： H01L21/28518 , H01L21/823814 , H01L21/823835
摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在用于容纳第一类型半导体器件的半导体衬底中形成第一阱区; 在所述半导体衬底中形成用于容纳第二类型半导体器件的第二阱区; 用掩模屏蔽第一类型半导体器件; 在所述第二类型半导体器件上沉积第一金属层; 在所述第二类型半导体器件上执行第一自对准硅化物形成; 去除面膜; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及在所述第一类型半导体器件上执行第二自对准硅化物形成。该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同硅化物材料的工艺。

18. 发明申请

US20080220581A1 OPTO-THERMAL ANNEALING METHODS FOR FORMING METAL GATE AND FULLY SILICIDED GATE-FIELD EFFECT TRANSISTORS 有权
标题翻译：用于形成金属门和完全硅化的栅极效应晶体管的光热退火方法
公开(公告)号：US20080220581A1
公开(公告)日：2008-09-11
申请号：US12120286
申请日：2008-05-14
申请人： Scott D. Allen , Cyril Cabral , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

19. 发明授权

US07410852B2 Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors 有权
标题翻译：用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法
公开(公告)号：US07410852B2
公开(公告)日：2008-08-12
申请号：US11408522
申请日：2006-04-21
申请人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/8234 , H01L21/42
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

20. 发明授权

US07317204B2 Test structure of semiconductor device 有权
标题翻译：半导体器件的测试结构
公开(公告)号：US07317204B2
公开(公告)日：2008-01-08
申请号：US11218397
申请日：2005-09-02
申请人： Min-chul Sun , Ja-hum Ku , Brian J. Greene , Manfred Eller , Wee Lang Tan , Sunfei Fang , Zhijiong Luo
发明人： Min-chul Sun , Ja-hum Ku , Brian J. Greene , Manfred Eller , Wee Lang Tan , Sunfei Fang , Zhijiong Luo
IPC分类号： H01L23/58
CPC分类号： H01L22/34
摘要： A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.
摘要翻译：提供半导体器件的测试结构。测试结构包括半导体衬底，晶体管，其包括形成在限定在半导体衬底内的第一和第二有源区上的栅极电极以及布置在栅电极的两个侧壁处以位于第一和第二有源区内的第一和第二接合区域，第二有源区，并且是硅化的，以及第一和第二焊盘，电信号通过该第一和第二焊盘施加到硅化的第一和第二结区，并被检测并形成在与栅电极或半导体衬底相同的高度上。

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