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11. 发明授权

US08645811B2 System and method for selective error checking 有权
标题翻译：选择性错误检查的系统和方法
公开(公告)号：US08645811B2
公开(公告)日：2014-02-04
申请号：US13283051
申请日：2011-10-27
申请人： William Sauber , Ayedin Nikazm , Stuart Allen Berke
发明人： William Sauber , Ayedin Nikazm , Stuart Allen Berke
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： H03M13/095 , G06F11/1004 , G06F21/53 , G06F21/64 , H03M13/09
摘要： A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information.
摘要翻译：一种选择性地启用信息处理系统中的错误检查的方法，包括接收指示与系统存储器中的第一存储器部分相关联的数据的信息应该在存储器控制器和系统存储器之间的传输期间进行错误检查，并指示数据相关联系统存储器中的第二存储器部分在存储器控制器和系统存储器之间的传输期间应该没有错误检查，接收指向第一和第二存储器部分之一的存储器访问请求，在存储器控制器和存储器控制器之间传送数据响应于存储器访问请求的系统存储器，并且基于该信息选择性地对发送的数据执行错误检查技术。

12. 发明申请

US20110131432A1 System and Method for Reducing Power Consumption of Memory 有权
标题翻译：降低内存功耗的系统和方法
公开(公告)号：US20110131432A1
公开(公告)日：2011-06-02
申请号：US12629681
申请日：2009-12-02
申请人： Stuart Allen Berke , William Sauber
发明人： Stuart Allen Berke , William Sauber
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F1/3203 , Y02D10/14
摘要： Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.
摘要翻译：公开了用于减少与存储器件中的功耗有关的问题和缺点的系统和方法。用于降低存储器中的功耗的方法可以包括通过在处理器上执行的操作系统跟踪正在使用的存储器系统的一个或多个逻辑单元。该方法还可以包括由操作系统基于正在使用的存储器系统的逻辑单元来设置指示正在使用的存储器系统的一部分的变量。该方法可以另外包括基于该变量刷新存储器系统的一个或多个逻辑单元中的一个或多个。

13. 发明授权

US09009407B2 System and method for performing system memory save in tiered/cached storage 有权
标题翻译：在分层/高速缓存存储器中执行系统内存的系统和方法
公开(公告)号：US09009407B2
公开(公告)日：2015-04-14
申请号：US13074958
申请日：2011-03-29
申请人： William Sauber , Mukund P. Khatri
发明人： William Sauber , Mukund P. Khatri
IPC分类号： G06F13/00 , G06F13/28 , G06F12/08 , G06F1/32
CPC分类号： G06F12/0804 , G06F1/26 , G06F1/3203 , G06F3/0619 , G06F3/0625 , G06F3/0634 , G06F3/0643 , G06F3/0647 , G06F3/0659 , G06F3/0685 , G06F3/0688 , G06F12/0895 , G06F2212/1032
摘要： In accordance with the present disclosure, a system and method for performing a system memory save in tiered or cached storage during transition to a decreased power state is disclosed. As disclosed herein, the system incorporating aspects of the present invention may include a flash or other nonvolatile memory such as a solid-state drive, volatile memory, and at least one alternate storage media. Upon transition to a decreased power state, at least some of the data in the solid-state drive, for example, may be transferred to the at least one alternate storage media. After the SSD data is transferred, data stored in volatile system memory, such as a system context, may be transferred to the SSD memory. With the system context saved in SSD memory, power to the volatile system memory may be turned off.
摘要翻译：根据本公开，公开了一种用于在转换到降低的功率状态期间执行分层或高速缓存的存储器中的系统存储器的系统和方法。如本文所公开的，结合本发明的方面的系统可以包括闪存或其他非易失性存储器，例如固态驱动器，易失性存储器和至少一个备用存储介质。在转换到降低的功率状态时，固态驱动器中的至少一些数据可以被传送到至少一个备用存储介质。在传输SSD数据之后，存储在诸如系统环境的易失性系统存储器中的数据可以被传送到SSD存储器。将系统上下文保存在SSD存储器中，可能会关闭易失性系统内存的电源。

14. 发明申请

US20070271477A1 SYSTEM AND METHOD FOR THROTTLING POWER IN ONE OR MORE INFORMATION HANDLING SYSTEMS 有权
标题翻译：用于在一个或多个信息处理系统中切断电力的系统和方法
公开(公告)号：US20070271477A1
公开(公告)日：2007-11-22
申请号：US11765351
申请日：2007-06-19
申请人： James Brewer , William Sauber
发明人： James Brewer , William Sauber
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： An information handling system includes support for dynamic power throttling. In one embodiment, an information handling system includes power level detection and power control modules. The power level detection module may monitor power consumption for the information handling system and may automatically transmit power level data to a power level manager, based on the monitored power consumption. The power control module may receive power control data from the power level manager. The power control module may also automatically adjust power consumption of the information handling system, in accordance with the power control data received from the power level manager. In another embodiment, an information handling system may include an interface and a power level manager. The power level manager may receive power information for computers via the interface, may automatically compute an adjusted power threshold setting, and may automatically transmit the adjusted power threshold setting to a computer.
摘要翻译：信息处理系统包括支持动态功率节流。在一个实施例中，信息处理系统包括功率电平检测和功率控制模块。功率电平检测模块可以监视信息处理系统的功率消耗，并且可以基于所监视的功率消耗自动地向功率电平管理器发送功率电平数据。功率控制模块可以从功率级管理器接收功率控制数据。功率控制模块还可以根据从功率电平管理器接收的功率控制数据自动调整信息处理系统的功耗。在另一个实施例中，信息处理系统可以包括接口和功率电平管理器。功率电平管理器可以通过接口接收计算机的功率信息，可以自动计算调整的功率阈值设置，并且可以自动地将调整的功率阈值设置发送到计算机。

15. 发明申请

US20060023883A1 System, method and apparatus for secure data transmissions within an information handling system 审中-公开
标题翻译：用于在信息处理系统内进行安全数据传输的系统，方法和装置
公开(公告)号：US20060023883A1
公开(公告)日：2006-02-02
申请号：US10899896
申请日：2004-07-27
申请人： David Konetski , William Sauber , Neeraj Srivastava
发明人： David Konetski , William Sauber , Neeraj Srivastava
IPC分类号： H04K1/00
CPC分类号： H04N21/43632 , G06F21/85 , H04N21/4113 , H04N21/4367
摘要： A system, method and apparatus are provided for creating a secure data path using a peer-to-peer enabled Peripheral Component Interconnect-Express (PCI-E) data communications path. In an exemplary implementation, a content receiver and rendering subsystem are provided, each aware of the other. The content receiver is operable to receive protected content from a source such as a set-top box. After authenticating the rendering subsystem as an approved content recipient, the content receiver preferably communicates decrypted content signals to the rendering subsystem via a peer-to-peer enabled PCI-E communications channel between the device systems. Once desired rendering processing operations have been performed on the decrypted content, the rendering subsystem may encrypt the rendered content before transmission to an associated display device for presentation.
摘要翻译：提供了一种系统，方法和装置，用于使用对等使能的外围组件互连Express（PCI-E）数据通信路径来创建安全数据路径。在示例性实现中，提供内容接收器和渲染子系统，每个都识别另一个。内容接收器可操作以从诸如机顶盒的源接收受保护的内容。在将呈现子系统认证为经批准的内容接收者之后，内容接收器优选地通过设备系统之间的对等使能的PCI-E通信信道将解密的内容信号传送到渲染子系统。一旦需要对解密的内容执行渲染处理操作，渲染子系统可以在传输到相关联的显示设备之前加密所渲染的内容以进行呈现。

16. 发明申请

US20050012747A1 Method and system for PCI express audiovisual output 有权
标题翻译：用于PCI视听输出的方法和系统
公开(公告)号：US20050012747A1
公开(公告)日：2005-01-20
申请号：US10621069
申请日：2003-07-16
申请人： William Sauber
发明人： William Sauber
IPC分类号： G06F3/14 , G06T1/00 , G09G5/00 , G09G5/36
CPC分类号： G06F3/14 , G09G5/006 , G09G5/363
摘要： A system and method for using a switch to route graphics data and data for a peripheral data on an interconnect is disclosed. A graphics card includes a switch that is communicatively coupled to a computer system. The switch receives graphics data and data for a peripheral device from the computer system via a first link. The switch routes the data for a peripheral device to a console via a second link and routes the graphics data to a graphics controller via a third link. The graphics controller forms a part of the graphics card and is communicatively coupled to the switch via the third link, wherein the graphics controller generates a video signal to drive a video display.
摘要翻译：公开了一种使用交换机在互连上路由外围数据的图形数据和数据的系统和方法。图形卡包括通信地耦合到计算机系统的交换机。交换机经由第一链路从计算机系统接收用于外围设备的图形数据和数据。交换机通过第二个链路将外围设备的数据路由到控制台，并通过第三个链路将图形数据路由到图形控制器。图形控制器形成图形卡的一部分，并且经由第三链接通信地耦合到开关，其中图形控制器产生视频信号以驱动视频显示。

17. 发明授权

US09251027B2 Information handling system performance optimization system 有权
标题翻译：信息处理系统性能优化系统
公开(公告)号：US09251027B2
公开(公告)日：2016-02-02
申请号：US13411911
申请日：2012-03-05
申请人： Munif Farhan , William Sauber
发明人： Munif Farhan , William Sauber
IPC分类号： G06F11/00 , G06F9/00 , G06F11/32 , G06F11/30 , G06F11/34
CPC分类号： G06F9/4401 , G06F11/3006 , G06F11/3093 , G06F11/328 , G06F11/3409
摘要： A performance optimization system includes a plurality of system components. A monitoring plug-in and a configuration plug-in are coupled to each of the plurality of system components. A monitoring engine receives monitoring information for each of the plurality of system components from their respective monitoring plug-in. A configuration engine sends configuration setting information to each of the plurality of system components through their respective configuration plug-ins. A performance optimization engine receives the monitoring information from the monitoring engine, determines a policy associated with the monitoring information and, in response, retrieves configuration setting information that is associated with the policy and sends the configuration setting information to the configuration engine in order to change the configuration of at least one of the plurality of system components.
摘要翻译：性能优化系统包括多个系统组件。监视插件和配置插件耦合到多个系统组件中的每一个。监控引擎从其各自的监控插件接收多个系统组件中的每一个的监控信息。配置引擎通过它们各自的配置插件向多个系统组件中的每一个发送配置设置信息。性能优化引擎从监视引擎接收监视信息，确定与监视信息相关联的策略，并且作为响应，检索与策略相关联的配置设置信息，并将配置设置信息发送到配置引擎以便改变所述多个系统组件中的至少一个的配置。

18. 发明授权

US08244995B2 System and method for hierarchical wear leveling in storage devices 有权
标题翻译：存储设备中分级磨损均衡的系统和方法
公开(公告)号：US08244995B2
公开(公告)日：2012-08-14
申请号：US12261723
申请日：2008-10-30
申请人： William Sauber
发明人： William Sauber
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7208 , G06F2212/7211
摘要： Systems and methods for reducing problems and disadvantages associated with wear leveling in storage devices are disclosed. A method may include maintaining module usage data associated with each of a plurality of storage device modules communicatively coupled to a channel. The method may also include maintaining device usage data associated with each of the plurality of storage devices associated with the storage device module for each of the plurality of storage device modules. The method may additionally include determining a particular storage device module of the plurality of storage device modules to which to store data associated with a write request based at least on the module usage data. The method may further include determining a particular storage device of the particular storage device module to which to store data associated with a write request based at least on the device usage data associated with the particular storage device module.
摘要翻译：公开了用于减少与存储设备中的磨损均衡相关的问题和缺点的系统和方法。方法可以包括维护与通信地耦合到信道的多个存储设备模块中的每一个相关联的模块使用数据。该方法还可以包括维护与多个存储设备模块中的每一个相关联的与存储设备模块相关联的多个存储设备中的每一个的设备使用数据。该方法可以另外包括：至少基于模块使用数据来确定用于存储与写请求相关联的数据的多个存储设备模块的特定存储设备模块。该方法还可以包括：至少基于与特定存储设备模块相关联的设备使用数据来确定特定存储设备模块的特定存储设备，用于存储与写入请求相关联的数据。

19. 发明授权

US08136024B2 Optional memory error checking 有权
标题翻译：可选内存错误检查
公开(公告)号：US08136024B2
公开(公告)日：2012-03-13
申请号：US12115645
申请日：2008-05-06
申请人： Ayedin Nikazm , William Sauber
发明人： Ayedin Nikazm , William Sauber
IPC分类号： G06F11/00 , G11C29/00
CPC分类号： G06F11/10
摘要： A memory error checking system includes a controller that is operable to transmit memory signals and error check signals. A first memory device coupler is coupled to the controller and operable to couple to a first memory device. The first memory device coupler is operable to transmit the memory signals from the controller to the first memory device. A first error check device coupler is coupled to the contoller and operable to couple to a first error check device that is separate from the first memory device. The first error check device coupler is operable to transmit the error check signals from the controller to the first error check device to be used to error check the memory signals transmitted to the first memory device.
摘要翻译：存储器错误检查系统包括可操作以发送存储器信号和错误检查信号的控制器。第一存储器件耦合器耦合到控制器并且可操作以耦合到第一存储器设备。第一存储器件耦合器可操作以将存储器信号从控制器传输到第一存储器件。第一错误检查设备耦合器耦合到控制器并且可操作以耦合到与第一存储器设备分离的第一错误检查设备。第一错误检查装置耦合器可操作以将来自控制器的错误检查信号发送到第一错误检查装置，以用于错误检查发送到第一存储器件的存储器信号。

20. 发明申请

US20050033970A1 System and method for securing access to memory modules 有权
标题翻译：用于确保访问内存模块的系统和方法
公开(公告)号：US20050033970A1
公开(公告)日：2005-02-10
申请号：US10634942
申请日：2003-08-05
申请人： Douglas Anson , Yuan-Chang Lo , Frank Molsberry , Clint O'Connor , William Sauber
发明人： Douglas Anson , Yuan-Chang Lo , Frank Molsberry , Clint O'Connor , William Sauber
IPC分类号： G06F12/14
CPC分类号： G06F12/1433
摘要： A system and method for securing access to memory modules includes a memory module, a virtual memory module, a boot module, and a gatekeeper. The boot module accepts a key and requests for the memory module and provides the requests and the key to the virtual memory module. The virtual memory module is externally accessible by the boot module and accepts the provided key and the requests from the boot module and transmits the requests and the provided key from the boot module to the gatekeeper. The gatekeeper regulates access to the memory module allowing no other components to directly access the memory module. The gatekeeper receives the provided key from the virtual memory module and the gatekeeper authenticates the provided key by comparing it with a stored key stored in secure location. Upon proper authentication of the provided key, the gatekeeper executes the request in the memory module.
摘要翻译：用于保护对存储器模块的访问的系统和方法包括存储器模块，虚拟存储器模块，引导模块和关守。引导模块接受密钥并请求内存模块，并将请求和密钥提供给虚拟内存模块。虚拟内存模块可由引导模块外部访问，并接受所提供的密钥和来自引导模块的请求，并将请求和提供的密钥从引导模块发送给关守。网守调节对内存模块的访问，允许其他组件直接访问内存模块。网守从虚拟存储器模块接收提供的密钥，并且关守通过将其与存储在安全位置中的存储密钥进行比较来认证所提供的密钥。对所提供的密钥进行适当认证后，网守将在存储器模块中执行该请求。

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