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11. 发明授权

US07581967B2 Connector with ESD protection 有权
标题翻译：带ESD保护的连接器
公开(公告)号：US07581967B2
公开(公告)日：2009-09-01
申请号：US11465045
申请日：2006-08-16
申请人： Patricio Collantes, Jr. , Robert C. Miller , Steven T. Sprouse , Dhaval Parikh
发明人： Patricio Collantes, Jr. , Robert C. Miller , Steven T. Sprouse , Dhaval Parikh
IPC分类号： H01R13/44
CPC分类号： H01R13/6485
摘要： A Universal Serial Bus flash memory unit having an electrically conductive housing includes a spring that provides an electrically conductive, low-resistance pathway between the housing and the metal shell of the Universal Serial Bus connector so that electrostatic charge can directly discharge from the housing to the metal shell instead of discharging through electronic components within the housing.
摘要翻译：具有导电壳体的通用串行总线闪速存储器单元包括弹簧，其在壳体和通用串行总线连接器的金属壳之间提供导电的低电阻通路，使得静电荷可以直接从壳体排出到金属外壳，而不是通过外壳内的电子元件放电。

12. 发明申请

US20080045056A1 Connector with ESD Protection 有权
标题翻译：带ESD保护的连接器
公开(公告)号：US20080045056A1
公开(公告)日：2008-02-21
申请号：US11465045
申请日：2006-08-16
申请人： Patricio Collantes, , Robert C. Miller , Steven T. Sprouse , Dhaval Parikh
发明人： Patricio Collantes, , Robert C. Miller , Steven T. Sprouse , Dhaval Parikh
IPC分类号： H01R13/44
CPC分类号： H01R13/6485
摘要： A Universal Serial Bus flash memory unit having an electrically conductive housing includes a spring that provides an electrically conductive, low-resistance pathway between the housing and the metal shell of the Universal Serial Bus connector so that electrostatic charge can directly discharge from the housing to the metal shell instead of discharging through electronic components within the housing.
摘要翻译：具有导电壳体的通用串行总线闪速存储器单元包括弹簧，其在壳体和通用串行总线连接器的金属壳之间提供导电的低电阻通路，使得静电荷可以直接从壳体排出到金属外壳，而不是通过外壳内的电子元件放电。

13. 发明申请

US20080045049A1 Methods for ESD Protection 有权
标题翻译： ESD保护方法
公开(公告)号：US20080045049A1
公开(公告)日：2008-02-21
申请号：US11465049
申请日：2006-08-16
申请人： Patricio Collantes , Robert C. Miller , Steven T. Sprouse , Dhaval Parikh
发明人： Patricio Collantes , Robert C. Miller , Steven T. Sprouse , Dhaval Parikh
IPC分类号： H05K1/00
CPC分类号： H05K9/0067 , H01R13/6582
摘要： A Universal Serial Bus flash memory unit having an electrically conductive housing includes a spring that provides an electrically conductive, low-resistance pathway between the housing and the metal shell of the Universal Serial Bus connector so that electrostatic charge can directly discharge from the housing to the metal shell instead of discharging through electronic components within the housing.
摘要翻译：具有导电壳体的通用串行总线闪速存储器单元包括弹簧，其在壳体和通用串行总线连接器的金属壳之间提供导电的低电阻通路，使得静电荷可以直接从壳体排出到金属外壳，而不是通过外壳内的电子元件放电。

14. 发明授权

US08995183B2 Data retention in nonvolatile memory with multiple data storage formats 有权
标题翻译：数据保存在具有多种数据存储格式的非易失性存储器中
公开(公告)号：US08995183B2
公开(公告)日：2015-03-31
申请号：US13453921
申请日：2012-04-23
申请人： Zac Shepard , Steven T. Sprouse , Chris Nga Yee Avila
发明人： Zac Shepard , Steven T. Sprouse , Chris Nga Yee Avila
IPC分类号： G11C11/34 , G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/349 , G11C2211/5641
摘要： In a nonvolatile memory that stores data in two or more different data storage formats, such as binary and MLC, a separation scheme is used to distribute blocks containing data in one data storage format (e.g. binary) so that they are separated by at least some minimum number of blocks using another data storage format (e.g. MLC).
摘要翻译：在将数据存储在诸如二进制和MLC之类的两种或多种不同数据存储格式的非易失性存储器中，分离方案用于分发包含一种数据存储格式（例如二进制）的数据的块，使得它们被至少一些使用其他数据存储格式的最小块数（例如MLC）。

15. 发明申请

US20130282958A1 Obsolete Block Management for Data Retention in Nonvolatile Memory 有权
标题翻译：非易失性存储器中数据保留的过时块管理
公开(公告)号：US20130282958A1
公开(公告)日：2013-10-24
申请号：US13453898
申请日：2012-04-23
申请人： Zac Shepard , Steven T. Sprouse , Chris Nga Yee Avila , Neil David Hutchison
发明人： Zac Shepard , Steven T. Sprouse , Chris Nga Yee Avila , Neil David Hutchison
IPC分类号： G06F12/00
CPC分类号： G06F12/0238 , G06F12/0246 , G11C5/005 , G11C11/5628 , G11C16/10 , G11C16/349
摘要： In a nonvolatile memory array, blocks that contain only obsolete data are modified by adding charge to their cells, increasing the charge level from the programmed charge levels that represented obsolete data to elevated charge levels. The increase in overall charge in such blocks lessens the tendency of such blocks to impact data retention in neighboring blocks.
摘要翻译：在非易失性存储器阵列中，仅包含过时数据的块通过向其单元添加电荷来修改，从将代表过时数据的程序化电荷电平增加到升高的电荷电平。这些块中的总体电荷的增加减少了这种块在相邻块中影响数据保留的趋势。

16. 发明申请

US20110161560A1 ERASE COMMAND CACHING TO IMPROVE ERASE PERFORMANCE ON FLASH MEMORY 审中-公开
标题翻译：删除命令缓存以提高闪速存储器的擦除性能
公开(公告)号：US20110161560A1
公开(公告)日：2011-06-30
申请号：US12651176
申请日：2009-12-31
申请人： Neil D. Hutchison , Alan D. Bennett , Sergey A. Gorobets , Steven T. Sprouse
发明人： Neil D. Hutchison , Alan D. Bennett , Sergey A. Gorobets , Steven T. Sprouse
IPC分类号： G06F12/02 , G06F12/10 , G06F17/30
CPC分类号： G06F12/0246 , G06F2212/1016 , G06F2212/7205 , G06F2212/7208
摘要： Systems and methods are disclosed to reduce the number of partial logical groups that are erased by writing erase patterns to memory in a non-volatile memory system. When a non-aligned erase command is received, the logical addresses of data associated with the erase command may be marked as erased. If the logical group corresponds to the size of a physical metablock, the controller may also issue a physical erase command for complete logical groups within the erase command. For those parts of the erase command that encompass only partial logical groups, the ranges of the logical block addresses marked for erasure are stored. As subsequent erase commands are received the address ranges of the erase commands are added to the previously stored address ranges. When a set of erase commands spans an entire logical group, the logical group is marked for physical erasure in its entirety.
摘要翻译：公开了系统和方法，以通过将擦除模式写入非易失性存储器系统中的存储器来减少擦除的部分逻辑组的数量。当接收到不对准的擦除命令时，可以将与擦除命令相关联的数据的逻辑地址标记为擦除。如果逻辑组对应于物理元区块的大小，则控制器还可以对擦除命令内的完整逻辑组发出物理擦除命令。对于仅包含部分逻辑组的擦除命令的那些部分，存储标记为擦除的逻辑块地址的范围。随着接下来的擦除命令被接收，擦除命令的地址范围被添加到先前存储的地址范围。当一组擦除命令跨越整个逻辑组时，逻辑组被整体标记为物理擦除。

17. 发明授权

US07564696B1 PCI bracket retainer for adapter card applications 有权
标题翻译：用于适配卡应用的PCI支架保持架
公开(公告)号：US07564696B1
公开(公告)日：2009-07-21
申请号：US11366844
申请日：2006-03-01
申请人： Alan L. Winick , Michael T. Milo , Steven T. Sprouse
发明人： Alan L. Winick , Michael T. Milo , Steven T. Sprouse
IPC分类号： H05K7/12
CPC分类号： G06F1/186
摘要： A bracket retainer is provided for securing an adapter card in a computer chassis in manner that maintains the electrical and the mechanical stability of the computer chassis and adapter card. This bracket retainer approach secures the adapter card to the computer chassis by utilizing a rotating door structure that allows the adapter card to be tightened into its card connector, as a rear tab of the adapter card, which is protruding through an opening of a rear panel of the computer chassis, is engaged by the rotating door structure. This bracket retainer approach also allows the bracket retainer to be secured to the computer chassis by interlocking the door structure with a top cover of the computer chassis.
摘要翻译：提供了一种支架保持器，用于将适配器卡固定在计算机机箱中，以保持计算机机箱和适配器卡的电气和机械稳定性。该支架固定器方法通过利用旋转门结构将适配器卡固定到计算机机箱，该旋转门结构允许将适配器卡紧固到其卡连接器中，作为适配器卡的后突出部，其通过后面板的开口突出的计算机机箱，由旋转门结构接合。该支架固定器方法还允许支架保持器通过将门结构与计算机机箱的顶盖互锁而固定到计算机机箱。

18. 发明授权

US06794997B2 Extending non-volatile memory endurance using data encoding 有权
标题翻译：使用数据编码扩展非易失性存储器耐久性
公开(公告)号：US06794997B2
公开(公告)日：2004-09-21
申请号：US10370413
申请日：2003-02-18
申请人： Steven T. Sprouse
发明人： Steven T. Sprouse
IPC分类号： H03M700
CPC分类号： H03M7/22 , G11C16/3495 , H03K21/403 , H03M7/16
摘要： An embedded system comprising a CPU and non-volatile memory is adapted to extend the endurance of the non-volatile memory through the use of an encoding of information stored in the non-volatile memory. One or more data bits are encoded into a larger number of non-volatile memory bit patterns such that changes to the data bits are distributed across fewer changes per non-volatile memory bit. Non-volatile memory endurance is extended since more changes to the data values are possible than can be supported by underlying changes to individual non-volatile memory bits. Word pre-erase, if present, can be accommodated as well as memory bit failures.
摘要翻译：包括CPU和非易失性存储器的嵌入式系统适于通过使用存储在非易失性存储器中的信息的编码来延长非易失性存储器的耐久性。一个或多个数据位被编码成更大数量的非易失性存储器位模式，使得对数据位的改变分布在每个非易失性存储器位更少的变化。非易失性存储器耐久性被扩展，因为数据值的更多变化可能比单个非易失性存储器位的底层变化可以支持。字预擦除（如果存在）可以适应以及存储器位故障。

19. 发明授权

US08732391B2 Obsolete block management for data retention in nonvolatile memory 有权
标题翻译：用于非易失性存储器中数据保留的过时块管理
公开(公告)号：US08732391B2
公开(公告)日：2014-05-20
申请号：US13453898
申请日：2012-04-23
申请人： Zac Shepard , Steven T. Sprouse , Chris Nga Yee Avila , Neil David Hutchison
发明人： Zac Shepard , Steven T. Sprouse , Chris Nga Yee Avila , Neil David Hutchison
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0238 , G06F12/0246 , G11C5/005 , G11C11/5628 , G11C16/10 , G11C16/349
摘要： In a nonvolatile memory array, blocks that contain only obsolete data are modified by adding charge to their cells, increasing the charge level from the programmed charge levels that represented obsolete data to elevated charge levels. The increase in overall charge in such blocks lessens the tendency of such blocks to impact data retention in neighboring blocks.
摘要翻译：在非易失性存储器阵列中，仅包含过时数据的块通过向其单元添加电荷来修改，从将代表过时数据的程序化电荷电平增加到升高的电荷电平。这些块中的总体电荷的增加减少了这种块在相邻块中影响数据保留的趋势。

20. 发明申请

US20120297121A1 Non-Volatile Memory and Method with Small Logical Groups Distributed Among Active SLC and MLC Memory Partitions 审中-公开
标题翻译：非易失性存储器和小逻辑组的方法分布在主动SLC和MLC内存分区中
公开(公告)号：US20120297121A1
公开(公告)日：2012-11-22
申请号：US13468720
申请日：2012-05-10
申请人： Sergey Anatolievich Gorobets , William S. Wu , Steven T. Sprouse
发明人： Sergey Anatolievich Gorobets , William S. Wu , Steven T. Sprouse
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/1044 , G06F2212/7202 , G06F2212/7203 , G06F2212/7205 , G06F2212/7208 , G11C2211/5641
摘要： A non-volatile memory organized into flash erasable blocks receives data from host writes by first staging into logical groups before writing into the blocks. Each logical group contains data from a predefined set of order logical addresses and has a fixed size smaller than a block. The totality of logical groups are obtained by partitioning a logical address space of the host into non-overlapping sub-ranges of ordered logical addresses, each logical group having a predetermined size within a range delimited by a minimum size of at least one page and a maximum size of fitting at least two logical groups in a block and up to an order of magnitude higher than a typical size of a host write. In this way, excessive garbage collection due to operating a large logical group is avoided while the address space is reduced to minimize the size of a caching RAM.
摘要翻译：组织成闪存可擦除块的非易失性存储器通过在写入块之前先进入逻辑组，从主机写入中接收数据。每个逻辑组包含来自预定义的一组订单逻辑地址的数据，并且具有小于块的固定大小。通过将主机的逻辑地址空间划分为有序逻辑地址的非重叠子范围来获得逻辑组的总和，每个逻辑组在由至少一个页面的最小大小限定的范围内具有预定大小，并且在块中拟合至少两个逻辑组的最大大小，并且高达主机写入的典型大小高达一个数量级。以这种方式，避免了由于操作大的逻辑组而导致的过多垃圾收集，同时减少了地址空间以最小化缓存RAM的大小。

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