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11. 发明申请

US20130232295A1 ADAPTIVE CACHE PROMOTIONS IN A TWO LEVEL CACHING SYSTEM 有权
公开(公告)号：US20130232295A1
公开(公告)日：2013-09-05
申请号：US13466861
申请日：2012-05-08
申请人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Ioannis Koltsidas , Roman A. Pletka
发明人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Ioannis Koltsidas , Roman A. Pletka
IPC分类号： G06F12/08
CPC分类号： G06F12/128 , G06F12/126
摘要： Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache.

12. 发明授权

US07669050B2 Method to enable user mode process to operate in a privileged execution mode 失效
标题翻译：允许用户模式进程在特权执行模式下运行的方法
公开(公告)号：US07669050B2
公开(公告)日：2010-02-23
申请号：US10877910
申请日：2004-06-24
申请人： Stephen L. Blinick , Yu-Cheng Hsu
发明人： Stephen L. Blinick , Yu-Cheng Hsu
IPC分类号： H04L29/06
CPC分类号： G06F9/468
摘要： A method to enable a user mode process to operate in a privileged execution mode is disclosed. Applicants' method provides an operating system comprising a privileged execution mode and a non-privileged execution mode, and a plurality of user mode strings operating in the non-privileged execution mode. The computing device receives a request from a first user mode string to operate in the privileged execution mode to perform one or more designated tasks. Applicants' method authorizes the first user mode string to operate in the privileged execution mode, and the first user mode string performs those one or more designated tasks using the privileged execution mode. Applicants' method continues to permit the first user mode string to operate in the privileged execution mode after completion of the one or more designated tasks.
摘要翻译：公开了一种使用户模式进程能够以特权执行模式运行的方法。申请人的方法提供包括特权执行模式和非特权执行模式的操作系统以及以非特权执行模式操作的多个用户模式串。计算设备接收来自第一用户模式串的请求，以在特权执行模式下操作以执行一个或多个指定的任务。申请人的方法授权第一用户模式字符串在特权执行模式下运行，第一用户模式字符串使用特权执行模式执行那些一个或多个指定任务。申请人的方法继续允许第一用户模式字符串在完成一个或多个指定任务之后以特权执行模式操作。

13. 发明申请

US20080155549A1 Method and Apparatus for Adjusting Sleep Time of Fixed High-Priority Threads 失效
标题翻译：调整固定高优先级线程睡眠时间的方法和装置
公开(公告)号：US20080155549A1
公开(公告)日：2008-06-26
申请号：US11613613
申请日：2006-12-20
申请人： Stephen L. Blinick , Scott A. Brewer , Chiahong Chen , Daniel A. Heffley , Radha K. Ramachandran
发明人： Stephen L. Blinick , Scott A. Brewer , Chiahong Chen , Daniel A. Heffley , Radha K. Ramachandran
IPC分类号： G06F9/46
CPC分类号： G06F9/485
摘要： A sleep function capable of putting a fixed high-priority thread to sleep within a time-window is disclosed. After a sleep request has been made by a fixed high-priority thread via the sleep function, a determination is made whether or not the fixed high-priority thread is awoken before a requested sleep duration under the sleep request. If the fixed high-priority thread is awoken before the requested sleep duration, the number of tasks for the fixed high-priority thread to perform is increased in order to delay the start sleep time of the fixed high-priority thread from a point within a first time-window in which the sleep request was made to an end boundary of the first time-window.
摘要翻译：公开了能够使固定的高优先级线程在时间窗内睡眠的睡眠功能。在通过睡眠功能由固定的高优先级线程进行了睡眠请求之后，确定在睡眠请求之前的所请求的睡眠持续时间之前固定的高优先级线程是否被唤醒。如果固定的高优先级线程在所请求的睡眠持续时间之前被唤醒，则增加固定高优先级线程的任务数量，以便将固定的高优先级线程的开始休眠时间从睡眠请求的第一个时间窗口到达第一个时间窗口的结束边界。

14. 发明授权

US08930624B2 Adaptive cache promotions in a two level caching system 有权
公开(公告)号：US08930624B2
公开(公告)日：2015-01-06
申请号：US13412412
申请日：2012-03-05
申请人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Ioannis Koltsidas , Roman A. Pletka
发明人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Ioannis Koltsidas , Roman A. Pletka
IPC分类号： G06F12/00 , G06F3/06
CPC分类号： G06F12/128 , G06F12/126
摘要： Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache.

15. 发明授权

US08136113B2 Method and apparatus for adjusting sleep time of fixed high-priority threads 失效
标题翻译：调整固定高优先级线程睡眠时间的方法和装置
公开(公告)号：US08136113B2
公开(公告)日：2012-03-13
申请号：US11613613
申请日：2006-12-20
申请人： Stephen L. Blinick , Scott A. Brewer , Chiahong Chen , Daniel A. Heffley , Radha K. Ramachandran
发明人： Stephen L. Blinick , Scott A. Brewer , Chiahong Chen , Daniel A. Heffley , Radha K. Ramachandran
IPC分类号： G06F9/46 , G06F13/24 , G06F9/44
CPC分类号： G06F9/485
摘要： A sleep function capable of putting a fixed high-priority thread to sleep within a time-window is disclosed. After a sleep request has been made by a fixed high-priority thread via the sleep function, a determination is made whether or not the fixed high-priority thread is awoken before a requested sleep duration under the sleep request. If the fixed high-priority thread is awoken before the requested sleep duration, the number of tasks for the fixed high-priority thread to perform is increased in order to delay the start sleep time of the fixed high-priority thread from a point within a first time-window in which the sleep request was made to an end boundary of the first time-window.
摘要翻译：公开了能够使固定的高优先级线程在时间窗内睡眠的睡眠功能。在通过睡眠功能由固定的高优先级线程进行了睡眠请求之后，确定在睡眠请求之前的所请求的睡眠持续时间之前固定的高优先级线程是否被唤醒。如果固定的高优先级线程在所请求的睡眠持续时间之前被唤醒，则增加固定高优先级线程的任务数量，以便将固定的高优先级线程的开始休眠时间从睡眠请求的第一个时间窗口到达第一个时间窗口的结束边界。

16. 发明授权

US07934045B2 Redundant and fault tolerant control of an I/O enclosure by multiple hosts 失效
标题翻译：多个主机对I / O机箱的冗余和容错控制
公开(公告)号：US07934045B2
公开(公告)日：2011-04-26
申请号：US12481401
申请日：2009-06-09
申请人： Stephen L. Blinick , John C. Elliott , Enrique Q. Garcia
发明人： Stephen L. Blinick , John C. Elliott , Enrique Q. Garcia
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： An apparatus, system, and method are disclosed for reliably controlling an I/O enclosure. A bus module receives two or more Peripheral Component Interconnect Express (“PCIe”) sideband signals via one or more PCIe cables. The one or more PCIe cables are connected between one or more hosts and an I/O enclosure. A decode module determines an asserted value of each of the two or more PCIe sideband signals and combines the PCIe sideband signal asserted values to form a bus value. Each PCIe sideband signal represents a bit in the bus value, and the bus value specifies a command for controlling the I/O enclosure. An execution module executes the specified command to perform control actions on the I/O enclosure.
摘要翻译：公开了用于可靠地控制I / O外壳的装置，系统和方法。总线模块经由一条或多条PCIe电缆接收两个或更多个外围组件互连Express（“PCIe”）边带信号。一个或多个PCIe电缆连接在一个或多个主机和I / O机箱之间。解码模块确定两个或多个PCIe边带信号中的每一个的有效值，并组合PCIe边带信号断言值以形成总线值。每个PCIe边带信号表示总线值中的一位，总线值指定用于控制I / O机箱的命令。执行模块执行指定的命令以对I / O机箱执行控制动作。

17. 发明申请

US20110087837A1 SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING 有权
标题翻译：用于写入累积和分析的二次高速缓存
公开(公告)号：US20110087837A1
公开(公告)日：2011-04-14
申请号：US12577164
申请日：2009-10-10
申请人： Stephen L. Blinick , Lokesh M. Gupta , Yu-Cheng Hsu , Cheng-Chung Song
发明人： Stephen L. Blinick , Lokesh M. Gupta , Yu-Cheng Hsu , Cheng-Chung Song
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F11/1008 , G06F11/1076 , G06F12/0866
摘要： A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed and claimed herein.
摘要翻译：本文公开了一种高效地使用大型二级高速缓存的方法。在某些实施例中，这种方法可以包括在二次高速缓存中累积多个数据轨道。这些数据轨道可以包括经修改的数据和/或未修改的数据。该方法可以确定多个数据轨道的一个子集是否构成一个完整的步幅。在子集构成一个完整的步骤的情况下，该方法可能会从二级缓存中退出该子集。通过降级整个步骤，该方法减少了从二级缓存中恢复数据所需的磁盘操作数。本文还公开并要求对应的计算机程序产品和装置。

18. 发明申请

US20100312942A1 Redundant and Fault Tolerant control of an I/O Enclosure by Multiple Hosts 失效
标题翻译：冗余和容错控制多个主机的I / O机箱
公开(公告)号：US20100312942A1
公开(公告)日：2010-12-09
申请号：US12481401
申请日：2009-06-09
申请人： Stephen L. Blinick , John C. Elliott , Enrique Q. Garcia
发明人： Stephen L. Blinick , John C. Elliott , Enrique Q. Garcia
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F2213/0026
摘要： An apparatus, system, and method are disclosed for reliably controlling an I/O enclosure. A bus module receives two or more Peripheral Component Interconnect Express (“PCIe”) sideband signals via one or more PCIe cables. The one or more PCIe cables are connected between one or more hosts and an I/O enclosure. A decode module determines an asserted value of each of the two or more PCIe sideband signals and combines the PCIe sideband signal asserted values to form a bus value. Each PCIe sideband signal represents a bit in the bus value, and the bus value specifies a command for controlling the I/O enclosure. An execution module executes the specified command to perform control actions on the I/O enclosure.
摘要翻译：公开了用于可靠地控制I / O外壳的装置，系统和方法。总线模块经由一条或多条PCIe电缆接收两个或更多个外围组件互连Express（“PCIe”）边带信号。一个或多个PCIe电缆连接在一个或多个主机和I / O机箱之间。解码模块确定两个或多个PCIe边带信号中的每一个的有效值，并组合PCIe边带信号断言值以形成总线值。每个PCIe边带信号表示总线值中的一位，总线值指定用于控制I / O机箱的命令。执行模块执行指定的命令以对I / O机箱执行控制动作。

19. 发明授权

US08972661B2 Dynamically adjusted threshold for population of secondary cache 有权
公开(公告)号：US08972661B2
公开(公告)日：2015-03-03
申请号：US13285740
申请日：2011-10-31
申请人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Ioannis Koltsidas , Roman A. Pletka
发明人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Ioannis Koltsidas , Roman A. Pletka
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0866 , G06F12/0897 , G06F2212/225
摘要： The population of data to be inserted into secondary data storage cache is controlled by determining a heat metric of candidate data; adjusting a heat metric threshold; rejecting candidate data provided to the secondary data storage cache whose heat metric is less than the threshold; and admitting candidate data whose heat metric is equal to or greater than the heat metric threshold. The adjustment of the heat metric threshold is determined by comparing a reference metric related to hits of data most recently inserted into the secondary data storage cache, to a reference metric related to hits of data most recently evicted from the secondary data storage cache; if the most recently inserted reference metric is greater than the most recently evicted reference metric, decrementing the threshold; and if the most recently inserted reference metric is less than the most recently evicted reference metric, incrementing the threshold.

20. 发明授权

US08935479B2 Adaptive cache promotions in a two level caching system 有权
标题翻译：二级缓存系统中的自适应缓存升级
公开(公告)号：US08935479B2
公开(公告)日：2015-01-13
申请号：US13466861
申请日：2012-05-08
申请人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Ioannis Koltsidas , Roman A. Pletka
发明人： Michael T. Benhase , Stephen L. Blinick , Evangelos S. Eleftheriou , Lokesh M. Gupta , Robert Haas , Xiao-Yu Hu , Ioannis Koltsidas , Roman A. Pletka
IPC分类号： G06F12/00 , G06F3/06
CPC分类号： G06F12/128 , G06F12/126
摘要： Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache.
摘要翻译：提供了一种用于管理第一高速缓存和第二高速缓存中的数据的计算机程序产品，系统和方法。当页面存储在第二高速缓存中时，对于页面的第二高速缓存中维护引用计数。确定页面将被从第二缓存提升到第一高速缓存。响应于确定参考计数大于零，该页被添加到第一高速缓存中的LRU列表的最近最少使用（LRU）末端。响应于确定参考计数小于或等于零，该页被添加到第一高速缓存中的LRU列表的最近使用（LRU）端。

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