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11. 发明授权

US08835318B2 HNO3 single wafer clean process to strip nickel and for MOL post etch 有权
标题翻译： HNO3单晶片清洁工艺，用于剥离镍和MOL后蚀刻
公开(公告)号：US08835318B2
公开(公告)日：2014-09-16
申请号：US13414946
申请日：2012-03-08
申请人： Clemens Fitz , Jochen Poth , Kristin Schupke
发明人： Clemens Fitz , Jochen Poth , Kristin Schupke
IPC分类号： H01L21/283 , H01L23/532
CPC分类号： H01L21/02068 , H01L21/28518 , H01L21/76829 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.
摘要翻译：通过在SWC工具中应用HNO3代替SPM清洗工艺，可以消除Ni和Pt残留物。实施例包括在半导体衬底上沉积一层Ni / Pt，对沉积的Ni / Pt层进行退火，通过在SWC工具中对退火的Ni / Pt层施加HNO 3，从退火的Ni / Pt层去除未反应的Ni，退火Ni 去除Ni / Pt层，并从退火的Ni去除的Ni / Pt层去除未反应的Pt。实施例包括在基板上形成第一和第二栅极电极，在每个栅电极的相对侧上形成间隔物，并在邻近每个间隔物的衬底上形成含Pt的NiSi，蚀刻间隔物，在第一栅电极上形成拉伸应变层，在SWC工具中的第一HNO 3，在第二栅电极上形成压应变层，并在SWC工具中施加第二HNO 3。

12. 发明授权

US08765586B2 Methods of forming metal silicide regions on semiconductor devices 有权
标题翻译：在半导体器件上形成金属硅化物区域的方法
公开(公告)号：US08765586B2
公开(公告)日：2014-07-01
申请号：US13331842
申请日：2011-12-20
申请人： Clemens Fitz , Peter Baars , Markus Lenski
发明人： Clemens Fitz , Peter Baars , Markus Lenski
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/28556 , H01L21/76814 , H01L29/41783 , H01L29/66545
摘要： Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.
摘要翻译：本文公开了在半导体器件上形成金属硅化物区域的各种方法。在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，在形成金属硅化物区域之后，执行选择性金属硅化物形成工艺以形成在衬底中或上方形成的源极/漏极区域中的金属硅化物区域，牺牲栅极结构以限定栅极开口并在栅极开口中形成替代栅极结构，所述替换栅极结构由至少一个金属层组成。

13. 发明授权

US08518765B1 Aqua regia and hydrogen peroxide HCl combination to remove Ni and NiPt residues 有权
标题翻译：水王和过氧化氢HCl组合去除Ni和NiPt残留物
公开(公告)号：US08518765B1
公开(公告)日：2013-08-27
申请号：US13489244
申请日：2012-06-05
申请人： Anh Duong , Clemens Fitz , Olov Karlsson
发明人： Anh Duong , Clemens Fitz , Olov Karlsson
IPC分类号： H01L21/336
CPC分类号： C11D11/0047 , C11D7/04 , C11D7/08 , C11D7/265 , H01L21/02057 , H01L21/02068 , H01L21/28052 , H01L21/324 , H01L21/6704 , H01L29/4975 , H01L29/66477 , H01L29/665 , H01L29/66568
摘要： A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.
摘要翻译：公开了一种在镍铂硅化过程中从半导体衬底中清除残余物的方法，包括多步残渣清洗，包括将底物暴露于王水溶液中，然后暴露于含有盐酸和过氧化氢的溶液中。 SC2溶液可以与剩余的铂残留物进一步反应，使其更易溶于水溶液，从而从基底表面溶解。

14. 发明授权

US08513117B2 Process to remove Ni and Pt residues for NiPtSi applications 有权
标题翻译：去除NiPtSi应用的Ni和Pt残留物的工艺
公开(公告)号：US08513117B2
公开(公告)日：2013-08-20
申请号：US13296444
申请日：2011-11-15
申请人： Anh Duong , Sean Barstow , Clemens Fitz , John Foster , Olov Karlsson , Bei Li , James Mavrinac
发明人： Anh Duong , Sean Barstow , Clemens Fitz , John Foster , Olov Karlsson , Bei Li , James Mavrinac
IPC分类号： H01L21/44
CPC分类号： H01L21/02068 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues.
摘要翻译：本发明公开了一种在镍铂硅化过程中清除半导体衬底的残留物的方法。本发明的实施方案提供了一种多步骤清洗方法，包括在第一次退火之后将基底暴露于硝酸溶液，然后在第二次退火之后暴露于王水溶液中。可以将底物任选地暴露于盐酸溶液中以完全除去任何剩余的铂残余物。

15. 发明申请

US20090057810A1 Method of Fabricating an Integrated Circuit 审中-公开
标题翻译：制造集成电路的方法
公开(公告)号：US20090057810A1
公开(公告)日：2009-03-05
申请号：US11850440
申请日：2007-09-05
申请人： Victor Verdugo , Dongping Wu , Clemens Fitz
发明人： Victor Verdugo , Dongping Wu , Clemens Fitz
IPC分类号： H01L21/8242 , H01L29/02
CPC分类号： H01L27/10894 , H01L27/10876
摘要： A method of fabricating an integrated circuit includes providing a semiconductor substrate having a doped area; generating a conductive structure towards the doped area, wherein the conductive structure includes an extending section that protrudes from the doped area; generating an electrically isolating layer at a sidewall of the extending section after generating the conductive structure.
摘要翻译：一种制造集成电路的方法包括：提供具有掺杂区域的半导体衬底; 向所述掺杂区域产生导电结构，其中所述导电结构包括从所述掺杂区域突出的延伸部分; 在产生导电结构之后，在延伸部分的侧壁处产生电绝缘层。

16. 发明授权

US08835298B2 NiSi rework procedure to remove platinum residuals 有权
标题翻译： NiSi返修程序去除铂残留物
公开(公告)号：US08835298B2
公开(公告)日：2014-09-16
申请号：US13415492
申请日：2012-03-08
申请人： Sivakumar Kumarasamy , Clemens Fitz , Markus Lenski , Jochen Poth , Kristin Schupke
发明人： Sivakumar Kumarasamy , Clemens Fitz , Markus Lenski , Jochen Poth , Kristin Schupke
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28518 , H01L22/12 , H01L22/20
摘要： The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni′/Pt layer at a temperature of 130° C.
摘要翻译：如果检测到Pt残留物，则通过执行包括在SWC工具中在130℃的温度下施加SPM的返工来减少形成含Pt的NiSi后剩余的Pt残余物的量。实施例包括在半导体衬底上沉积一层Ni / Pt，退火沉积的Ni / Pt层，从退火的Ni / Pt层去除未反应的Ni，退火Ni去除的Ni / Pt层，从退火的Ni中除去未反应的Pt Ni / Pt层，分析未去除Pt残留物的Pt去除Ni / Pt层，如果检测到未反应的Pt残留物，则在SWC工具中将Pt施加到去除的Pt / Ni层上。可以在130℃的温度下将SPM施加到Pt去除的Ni'/ Pt层上

17. 发明申请

US20130234335A1 HNO3 SINGLE WAFER CLEAN PROCESS TO STRIP NICKEL AND FOR MOL POST ETCH 有权
标题翻译： HNO3单辊清洗工艺，用于粘合镍和MOL POST ETCH
公开(公告)号：US20130234335A1
公开(公告)日：2013-09-12
申请号：US13414946
申请日：2012-03-08
申请人： Clemens Fitz , Jochen Poth , Kristin Schupke
发明人： Clemens Fitz , Jochen Poth , Kristin Schupke
IPC分类号： H01L23/532 , H01L21/283
CPC分类号： H01L21/02068 , H01L21/28518 , H01L21/76829 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO3 in an SWC tool. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer by applying HNO3 to the annealed Ni/Pt layer in an SWC tool, annealing the Ni removed Ni/Pt layer, and removing unreacted Pt from the annealed Ni removed Ni/Pt layer. Embodiments include forming first and second gate electrodes on a substrate, spacers on opposite sides of each gate electrode, and Pt-containing NiSi on the substrate adjacent each spacer, etching back the spacers, forming a tensile strain layer over the first gate electrode, applying a first HNO3 in an SWC tool, forming a compressive strain layer over the second gate electrode, and applying a second HNO3 in an SWC tool.
摘要翻译：通过在SWC工具中应用HNO3代替SPM清洗工艺，可以消除Ni和Pt残留物。实施例包括在半导体衬底上沉积一层Ni / Pt，对沉积的Ni / Pt层进行退火，通过在SWC工具中对退火的Ni / Pt层施加HNO 3，从退火的Ni / Pt层去除未反应的Ni，退火Ni 去除Ni / Pt层，并从退火的Ni去除的Ni / Pt层去除未反应的Pt。实施例包括在基板上形成第一和第二栅极电极，在每个栅电极的相对侧上形成间隔物，并在邻近每个间隔物的衬底上形成含Pt的NiSi，蚀刻间隔物，在第一栅电极上形成拉伸应变层，在SWC工具中的第一HNO 3，在第二栅电极上形成压应变层，并在SWC工具中施加第二HNO 3。

18. 发明申请

US20100090285A1 Integrated Circuit with a Contact Structure Including a Portion Arranged in a Cavity of a Semiconductor Structure 有权
标题翻译：具有包含在半导体结构的腔中的部分的接触结构的集成电路
公开(公告)号：US20100090285A1
公开(公告)日：2010-04-15
申请号：US12251864
申请日：2008-10-15
申请人： Werner Graf , Clemens Fitz
发明人： Werner Graf , Clemens Fitz
IPC分类号： H01L27/088 , H01L23/48 , H01L21/76
CPC分类号： H01L21/743 , H01L21/823418 , H01L21/823475 , H01L23/485 , H01L29/66636 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding second portion is arranged above the main surface of the semiconductor structure and in direct contact with a conductive structure that is spaced apart from or separated from the main surface of the semiconductor structure. An insulator structure is arranged below and in direct contact with the contact structure.
摘要翻译：集成电路包括具有埋入的第一和突出的第二部分的接触结构。掩埋的第一部分布置在形成于半导体结构中并与半导体结构直接接触的空腔中。突出的第二部分布置在半导体结构的主表面上方，并且与与半导体结构的主表面间隔开或分离的导电结构直接接触。绝缘体结构布置在接触结构的下方并直接接触。

19. 发明授权

US07679149B2 Method of removing refractory metal layers and of siliciding contact areas 失效
$Method of removing refractory metal layers and of siliciding contact areas$
标题翻译：去除难熔金属层和硅化接触区域的方法
公开(公告)号：US07679149B2
公开(公告)日：2010-03-16
申请号：US11669500
申请日：2007-01-31
申请人： Audrey Beckert , Matthias Goldbach , Clemens Fitz
发明人： Audrey Beckert , Matthias Goldbach , Clemens Fitz
IPC分类号： H01L29/76
CPC分类号： H01L21/28518 , H01L21/32134 , H01L21/76843 , H01L21/76855 , H01L29/66545 , H01L29/78
摘要： A method of formation of contacts with cobalt silicide since is disclosed. For example, after siliciding with the SOM solution, both unreacted sections of the deposition layer including, for example, cobalt as initial layer for the siliciding and an oxidation protection layer including titanium and deposited by means of cathode beam sputtering, for instance, may be removed rapidly and with high selectivity relative to the cobalt silicide and other, densified metal structures and metal layers.
摘要翻译：公开了一种与硅化钴形成接触的方法。例如，在用SOM溶液硅化后，例如包括例如作为硅化的初始层的钴的钴的沉积层的未反应部分和包括钛并通过阴极射线溅射沉积的氧化保护层可以是相对于硅化钴和其它致密的金属结构和金属层，快速且高选择性地去除。

20. 发明授权

US07678654B2 Buried bitline with reduced resistance 失效
标题翻译：埋伏的位线减少阻力
公开(公告)号：US07678654B2
公开(公告)日：2010-03-16
申请号：US11478313
申请日：2006-06-30
申请人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Müller , Hocine Boubekeur
发明人： Christoph Kleint , Clemens Fitz , Ulrike Bewersdorff-Sarlette , Christoph Ludwig , David Pritchard , Torsten Müller , Hocine Boubekeur
IPC分类号： H01L21/8247 , H01L29/792
CPC分类号： G11C5/063 , G11C7/18 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.
摘要翻译：存储单元阵列包括多个存储单元，每个存储单元包括由半导体衬底内的相应位线限定的源极和漏极区域。每个位线具有掺杂半导体区域以及与掺杂半导体区域直接电接触的导电区域。

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