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11. 发明授权

US08624398B2 Semiconductor circuit structure 有权
标题翻译：半导体电路结构
公开(公告)号：US08624398B2
公开(公告)日：2014-01-07
申请号：US12547521
申请日：2009-08-26
申请人： Chia-Chen Sun , Shih-Chieh Hsu , Yi-Chung Sheng , Sheng-Yuan Hsueh , Yao-Chang Wang
发明人： Chia-Chen Sun , Shih-Chieh Hsu , Yi-Chung Sheng , Sheng-Yuan Hsueh , Yao-Chang Wang
IPC分类号： H01L23/52
CPC分类号： G06F17/5081 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit structure includes a substrate and an interconnect structure. The interconnect structure is disposed on the substrate and includes a plurality of circuit patterns and at least one closed loop pattern. The closed loop pattern is in a same layer with the circuit patterns, surrounds between the circuit patterns and is insulated from the circuit patterns. The closed loop pattern can protect the circuit patterns from being damaged by stresses, for improving a mechanical strength of the semiconductor circuit structure.
摘要翻译：半导体电路结构包括基板和互连结构。互连结构设置在衬底上并且包括多个电路图案和至少一个闭环图案。闭环图案与电路图案处于相同的层中，在电路图案之间包围并与电路图案绝缘。闭环图案可以保护电路图案不被应力损坏，以改善半导体电路结构的机械强度。

12. 发明授权

US6103606A Method of fabricating a word line 失效
标题翻译：制作字线的方法
公开(公告)号：US6103606A
公开(公告)日：2000-08-15
申请号：US727089
申请日：1996-10-07
申请人： Der-Yuan Wu , Yi-Chung Sheng
发明人： Der-Yuan Wu , Yi-Chung Sheng
IPC分类号： H01L21/28 , H01L21/768 , H01L21/3205 , H01L21/44 , H01L23/48 , H01L27/108
CPC分类号： H01L21/28061 , H01L21/76886
摘要： On a substrate with a number rows of gates are formed. After a metal silicide layer is formed above the gates, a silicon-rich layer is formed. The silicon-rich layer is either a further metal silicide layer, with a higher silicon concentration or a pure silicon layer.
摘要翻译：在具有数排栅极的衬底上形成。在栅极之上形成金属硅化物层之后，形成富硅层。富硅层是另一金属硅化物层，具有较高的硅浓度或纯硅层。

13. 发明授权

US5504030A Process for fabricating high-density mask ROM devices 失效
标题翻译：制造高密度掩模ROM器件的工艺
公开(公告)号：US5504030A
公开(公告)日：1996-04-02
申请号：US505050
申请日：1995-07-21
申请人： Chen-Hui Chung , Kuan-Cheng Su , Yi-Chung Sheng
发明人： Chen-Hui Chung , Kuan-Cheng Su , Yi-Chung Sheng
IPC分类号： H01L21/8246
CPC分类号： H01L27/11246 , Y10S438/981
摘要： A method of fabricating memory cells of a mask ROM device. A plurality of source/drain regions extending along a first direction is formed by implanting impurities into a semiconductor substrate, constituting bit lines of the memory cells. A code oxide layer is formed on a designated area of the semiconductor substrate defined by a barrier layer using a liquid-phase deposition process, whereby a multi-state mask ROM is fabricated by repeatedly performing the liquid-phase deposition process to form a series of coding oxide layers having increasing thicknesses. A gate oxide layer is formed on a portion of the semiconductor substrate not covered by the coding oxide layers. The thickness of the gate oxide layer is smaller than that of the coding oxide layers. A plurality of gate electrodes extending along a second direction orthogonal to the first direction is formed by depositing and patterning a conducting layer on the coding oxide layer and the gate oxide layer, constituting word lines of said memory cells. The cross area of every two adjacent bit lines and one word line thereby forms a memory cell of the mask ROM wherein threshold voltages of the memory cells are altered proportional to the thicknesses of the gate oxide layer and the coding oxide layers.
摘要翻译：一种制造掩模ROM器件的存储单元的方法。沿着第一方向延伸的多个源极/漏极区域通过将杂质注入构成存储器单元的位线的半导体衬底中而形成。在通过液相沉积工艺由阻挡层限定的半导体衬底的指定区域上形成编码氧化物层，由此通过反复进行液相沉积工艺以形成一系列编码具有增加的厚度的氧化物层。在不被编码氧化物层覆盖的半导体衬底的一部分上形成栅氧化层。栅极氧化物层的厚度小于编码氧化物层的厚度。通过在构成所述存储单元的字线的编码氧化物层和栅极氧化物层上沉积和图案化导电层来形成沿着与第一方向正交的第二方向延伸的多个栅电极。因此，每两个相邻位线和一个字线的横截面形成掩模ROM的存储单元，其中存储单元的阈值电压与栅极氧化物层和编码氧化物层的厚度成比例地变化。

14. 发明授权

US08207043B2 Method for fabricating a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08207043B2
公开(公告)日：2012-06-26
申请号：US12568657
申请日：2009-09-28
申请人： Huang-Yi Lin , Jiun-Hung Shen , Chi-Horn Pai , Yi-Chung Sheng , Shih-Chieh Hsu
发明人： Huang-Yi Lin , Jiun-Hung Shen , Chi-Horn Pai , Yi-Chung Sheng , Shih-Chieh Hsu
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/26506 , H01L21/26513 , H01L21/268 , H01L29/6656 , H01L29/6659 , H01L29/7847
摘要： A method for making a semiconductor MOS device is provided. A gate structure is formed on a substrate. A source and a drain are formed in the substrate on both sides of the gate structure. The substrate is then subjected to a pre-amorphization implant (PAI) process. A transitional stress layer is then formed on the substrate. Thereafter, a laser anneal with a first temperature is performed. After the laser anneal, a rapid thermal process is performed with a second temperature that is lower than the first temperature. Subsequently, the transitional stress layer is removed.
摘要翻译：提供了制造半导体MOS器件的方法。在基板上形成栅极结构。源极和漏极形成在栅极结构两侧的衬底中。然后将基材进行预非晶化植入（PAI）工艺。然后在衬底上形成过渡应力层。此后，进行具有第一温度的激光退火。在激光退火之后，以低于第一温度的第二温度进行快速热处理。随后，去除过渡应力层。

15. 发明授权

US07932104B2 Method for inspecting photoresist pattern 有权
标题翻译：检测光刻胶图案的方法
公开(公告)号：US07932104B2
公开(公告)日：2011-04-26
申请号：US12468063
申请日：2009-05-19
申请人： Chia-Chen Sun , Yi-Chung Sheng , Sheng-Yuan Hsueh
发明人： Chia-Chen Sun , Yi-Chung Sheng , Sheng-Yuan Hsueh
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , G03F7/70658 , H01L22/14
摘要： A method for inspecting a photoresist pattern is disclosed. First, a substrate with a first doping region is provided. Then, a photoresist is formed to cover the substrate. Later, the photoresist is patterned to form a photoresist pattern. Afterwards, the substrate is doped by using the photoresist pattern, and a PN junction exists in the first doping region. Thereafter, a current passing through the PN junction is tested to inspect the photoresist pattern.
摘要翻译：公开了一种用于检查光致抗蚀剂图案的方法。首先，提供具有第一掺杂区域的衬底。然后，形成光致抗蚀剂以覆盖基板。之后，将光致抗蚀剂图案化以形成光致抗蚀剂图案。之后，通过使用光致抗蚀剂图案来掺杂衬底，并且PN结存在于第一掺杂区域中。此后，测试通过PN结的电流，以检查光刻胶图案。

16. 发明授权

US5654576A Post-titanium nitride mask ROM programming method and device manufactured thereby 失效
标题翻译：后氮化钛掩模ROM编程方法和由此制造的器件
公开(公告)号：US5654576A
公开(公告)日：1997-08-05
申请号：US559324
申请日：1995-11-16
申请人： Chen-Chiu Hsue , Yi-Chung Sheng , Shing-Ren Sheu , Chen-Hui Chung
发明人： Chen-Chiu Hsue , Yi-Chung Sheng , Shing-Ren Sheu , Chen-Hui Chung
IPC分类号： H01L21/8246 , H01L27/112 , H01L29/94
CPC分类号： H01L27/1126 , H01L27/112 , Y10S257/915
摘要： A method of manufacturing a code pattern on a semiconductor substrate with an array of substantially parallel buried bit lines integral therewith and with word lines above the buried bit lines, includes: forming a titanium nitride layer above the word lines, forming and patterning a code mask above the titanium nitride layer, implanting impurities into the substrate through openings in the code mask to form the code pattern, and performing rapid thermal annealing of the implant. The step height of the titanium nitride layer is employed to form the code identification on the substrate.
摘要翻译：一种在半导体衬底上制造具有与其一体的基本上平行的掩埋位线阵列和掩埋位线之上的字线的阵列的方法，包括：在字线之上形成氮化钛层，形成码图掩模在氮化钛层之上，通过编码掩模中的开口将杂质注入到衬底中，以形成编码图案，并对植入物进行快速热退火。氮化钛层的台阶高度用于在基板上形成代码识别。

17. 发明授权

US5545580A Multi-state read-only memory using multiple polysilicon selective depositions 失效
标题翻译：多状态只读存储器，使用多个多晶硅选择性沉积
公开(公告)号：US5545580A
公开(公告)日：1996-08-13
申请号：US530746
申请日：1995-09-19
申请人： Yi-Chung Sheng , Chen-Hui Chung , Kuan-Cheng Su
发明人： Yi-Chung Sheng , Chen-Hui Chung , Kuan-Cheng Su
IPC分类号： H01L27/112 , H01L21/8246
CPC分类号： H01L27/112
摘要： A multi-state read-only-memory device and a method for fabricating the same is suitable for forming on a semiconductor substrate. The read-only memory device is provided with bit lines and word lines which are mutually intersecting. In accordance with the present invention, multiple polysilicon selective deposition procedures are utilized to form a plurality of protrusion portions onto the word lines but with multiple thicknesses. Then, one implantation procedure is applied to program the device into multiple states at the same time without incurring misalignment problems that result in inaccuracy.
摘要翻译：多状态只读存储器件及其制造方法适用于在半导体衬底上形成。只读存储器件具有相互相交的位线和字线。根据本发明，利用多个多晶硅选择性沉积程序在字线上形成多个突出部分，但具有多个厚度。然后，应用一个植入程序同时将器件编程成多个状态，而不会导致导致不准确的错位问题。

18. 发明申请

US20130277754A1 Semiconductor Integrated Structure 审中-公开
标题翻译：半导体集成结构
公开(公告)号：US20130277754A1
公开(公告)日：2013-10-24
申请号：US13451540
申请日：2012-04-20
申请人： Chia-Wen Liang , Yi-Chung Sheng , Shih-Chieh Hsu , Yao-Chang Wang , Chi-Horn Pai , Jie-Ning Yang , Chi-Sheng Tseng
发明人： Chia-Wen Liang , Yi-Chung Sheng , Shih-Chieh Hsu , Yao-Chang Wang , Chi-Horn Pai , Jie-Ning Yang , Chi-Sheng Tseng
IPC分类号： H01L27/06
CPC分类号： H01L27/0629
摘要： The present invention provides a resistor structure including a substrate, an ILD layer, a transistor and a resistor. The substrate includes a resistor region and an active region. The ILD layer is disposed directly on the substrate. The transistor is disposed in the active region in the ILD layer wherein the transistor includes a metal gate. The resistor is disposed in the resistor region above the ILD layer, wherein the resistor directly contacts the ILD layer.
摘要翻译：本发明提供一种包括衬底，ILD层，晶体管和电阻器的电阻器结构。衬底包括电阻器区域和有源区域。 ILD层直接设置在基板上。晶体管设置在ILD层中的有源区中，其中晶体管包括金属栅极。电阻器设置在ILD层上方的电阻器区域中，其中电阻器直接接触ILD层。

19. 发明申请

US20110049722A1 Semiconductor Circuit Structure and Layout Method thereof 有权
标题翻译：半导体电路结构及其布局方法
公开(公告)号：US20110049722A1
公开(公告)日：2011-03-03
申请号：US12547521
申请日：2009-08-26
申请人： Chia-Chen Sun , Shih-Chieh Hsu , Yi-Chung Sheng , Sheng-Yuan Hsueh , Yao-Chang Wang
发明人： Chia-Chen Sun , Shih-Chieh Hsu , Yi-Chung Sheng , Sheng-Yuan Hsueh , Yao-Chang Wang
IPC分类号： H01L23/52 , G06F17/50
CPC分类号： G06F17/5081 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor circuit structure includes a substrate and an interconnect structure. The interconnect structure is disposed on the substrate and includes a plurality of circuit patterns and at least one closed loop pattern. The closed loop pattern is in a same layer with the circuit patterns, surrounds between the circuit patterns and is insulated from the circuit patterns. The closed loop pattern can protect the circuit patterns from being damaged by stresses, for improving a mechanical strength of the semiconductor circuit structure.
摘要翻译：半导体电路结构包括基板和互连结构。互连结构设置在衬底上并且包括多个电路图案和至少一个闭环图案。闭环图案与电路图案处于相同的层中，在电路图案之间包围并与电路图案绝缘。闭环图案可以保护电路图案不被应力损坏，以改善半导体电路结构的机械强度。

20. 发明申请

US20070042584A1 METHOD OF FORMING A SILICIDE 审中-公开
公开(公告)号：US20070042584A1
公开(公告)日：2007-02-22
申请号：US11161756
申请日：2005-08-16
申请人： Jen-Hong Huang , Nien-Chung Li , Yi-Chung Sheng , Chun-Chia Chen
发明人： Jen-Hong Huang , Nien-Chung Li , Yi-Chung Sheng , Chun-Chia Chen
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L29/6653 , H01L29/6656
摘要： At least one gate electrode is formed on a substrate. A first dielectric layer and a second dielectric layer are formed on the gate electrode, respectively. A portion of the second dielectric layer is removed to form a spacer on either side of the gate electrode. A portion of the first dielectric layer is removed to form a notch between the gate electrode and the spacer, the notch having an aspect ratio greater than 1. A self-aligned silicide process is performed to form a silicide on exposed surfaces of the gate electrode and the first dielectric layer underneath the notch.

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