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    • 12. 发明申请
    • Combination dosing regimen for erythropoietin
    • 红细胞生成素联合给药方案
    • US20050267026A1
    • 2005-12-01
    • US11088284
    • 2005-03-24
    • Wing Cheung
    • Wing Cheung
    • A61K38/18
    • A61K38/1816
    • The present invention provides a combination dosing regimen for erythropoietin (EPO). More particularly, the present dosing regimen includes administration of at least a first dosing segment comprising a first exposure to EPO capable of stimulating the production of reticulocytes followed by a second exposure to EPO capable of sustaining the maturation of the reticulocytes into neocytes, and ultimately, red blood cells. Advantageously, the dosing segment may be cycled or repeated, any number of times and according to any desired time scheme, in order to provide or maintain any desired total red blood cell count and/or hemoglobin concentration. Methods of treatment employing the combination dosing regimen, as well as kits are also provided.
    • 本发明提供促红细胞生成素(EPO)的组合给药方案。 更具体地,本发明的给药方案包括施用至少第一给药段,其包含能够刺激网织红细胞生成的EPO的第一次暴露,然后第二次暴露于能够维持网织红细胞成熟为新细胞的EPO, 红细胞。 有利地,给药段可以循环或重复任意次数,并且根据任何期望的时间方案,以便提供或维持任何期望的总红细胞计数和/或血红蛋白浓度。 还提供了使用联合给药方案的治疗方法以及试剂盒。
    • 14. 发明授权
    • Apparatus and method for performing look-ahead scheduling of DMA
transfers of data from a host memory to a transmit buffer memory
    • 用于执行从主机存储器到发送缓冲存储器的数据DMA传输的预先调度的装置和方法
    • US5970229A
    • 1999-10-19
    • US707896
    • 1996-09-12
    • Robert E. ThomasPeter J. RomanWing Cheung
    • Robert E. ThomasPeter J. RomanWing Cheung
    • G06F13/38G06F13/00
    • G06F13/387
    • An apparatus and method for transferring data from a source memory (e.g. a host memory) to a peripheral interface via a bus utilizes a transmit buffer memory coupled to the peripheral interface, and a current time counter advancing at the rate at which data is to be transferred from the transmit buffer memory to the peripheral interface. A schedule table data structure stores entries in some or all of its locations, where each location corresponds to a point in time at which data is to be transferred from the transmit buffer memory to the peripheral interface. A schedule table pointer is used for pointing to successive locations in the schedule table. The schedule table pointer advances at a rate faster than the current time counter advances so that the schedule table pointer represents a point in time which is ahead of the point in time currently output by the current time counter. A data transfer is initiated from the source memory to the transmit buffer memory via the bus when a valid entry is stored at the location in the schedule table pointed to by the schedule table pointer. The data is then transferred out of the transmit buffer memory to the peripheral interface when the current time counter reaches the value representing at least the same point in time that was represented by the schedule table pointer when the data transfer was initiated. Data transfers from the transmit buffer memory are thereby synchronized in time with their corresponding entries in the schedule table.
    • 用于经由总线将数据从源存储器(例如,主机存储器)传送到外围接口的装置和方法利用耦合到外围接口的发送缓冲存储器和以数据的速率前进的当前时间计数器 从发送缓冲存储器传送到外设接口。 调度表数据结构存储其部分或全部位置中的条目,其中每个位置对应于将数据从发送缓冲存储器传送到外围接口的时间点。 调度表指针用于指向调度表中的连续位置。 调度表指针以比当前时间计数器更快的速率前进,使得调度表指针表示在当前时间计数器当前输出的时间点之前的时间点。 当有效条目存储在调度表指针指向的调度表中的位置时,通过总线从源存储器发送到发送缓冲存储器的数据传输。 然后,当当前时间计数器达到表示数据传输启动时由调度表指针表示的至少相同的时间点的值时,将数据传送到发送缓冲存储器中的外设接口。 因此,从发送缓冲存储器的数据传输在时间上与其在调度表中的相应条目同步。
    • 15. 发明授权
    • Apparatus and method for transferring data from a transmit buffer memory
at a particular rate
    • 用于以特定速率从发送缓冲存储器传送数据的装置和方法
    • US5941952A
    • 1999-08-24
    • US712687
    • 1996-09-12
    • Robert E. ThomasPeter J. RomanWing Cheung
    • Robert E. ThomasPeter J. RomanWing Cheung
    • H04L12/56H04Q11/04G06F13/38G06F15/17
    • H04Q11/0478H04L2012/5616H04L2012/5635H04L2012/5658H04L2012/5664H04L2012/5667H04L2012/5679H04L2012/5681
    • An apparatus and method for transferring data from a source memory to a transmit buffer memory and then from the transmit buffer memory at a particular rate. A current time counter advances at the rate at which data is to be transmitted from the transmit buffer memory to the interface. A schedule memory stores entries, each valid entry being associated with data that is to be transmitted from the transmit buffer memory to the interface. A timestamp is associated with each valid entry in the schedule memory. Circuitry is then operative on each valid entry read from the schedule table to generate a request for a data transfer between the source memory and the transmit buffer memory; perform a data transfer from the source memory to the transmit buffer memory in response to the request; and transfer the data from the transmit buffer memory when the current time circuitry output reaches a value representing at least the same point in time that is represented by the timestamp associated with the entry for which the request was generated.
    • 一种用于将数据从源存储器传送到发送缓冲存储器然后以特定速率从发送缓冲存储器传送的装置和方法。 当前时间计数器以数据从发送缓冲存储器发送到接口的速率前进。 调度存储器存储条目,每个有效条目与要从发送缓冲存储器发送到接口的数据相关联。 时间戳与调度存储器中的每个有效条目相关联。 然后对从调度表读取的每个有效条目进行电路以产生对源存储器和发送缓冲存储器之间的数据传输的请求; 响应于该请求,执行从源存储器到发送缓冲存储器的数据传输; 并且当当前时间电路输出达到表示与由生成请求的条目相关联的时间戳表示的至少相同的时间点的值时,传送来自发送缓冲存储器的数据。
    • 19. 发明授权
    • Method and apparatus for performing TX raw cell status report frequency and interrupt frequency mitigation in a network node
    • 用于在网络节点中执行TX原始小区状态报告频率和中断频率减轻的方法和装置
    • US06466997B1
    • 2002-10-15
    • US09332836
    • 1999-06-14
    • Theodore L. RossDouglas M. WashabaughPeter J. RomanWing CheungKoichi TanakaShinichi MizuguchiRobert E. Thomas
    • Theodore L. RossDouglas M. WashabaughPeter J. RomanWing CheungKoichi TanakaShinichi MizuguchiRobert E. Thomas
    • G06F500
    • G06F13/387H04L2012/5616H04L2012/5658
    • A method and system for requesting an interrupt from a host system to service an adapter connected to the host system and a data interface. Data packets, including one or more data cells, are transferred between the data interface and the host system. The host system includes a host memory that includes a plurality of memory slots to store data packets transferred between the data interface and the host system. It is determined when a transfer of data has resulted in an occurrence of an interrupt event. An interrupt event occurs when the transfer of data includes a transfer of a data cell between the data interface and the host system and the data cell is defined to be an end of a data packet. In response to the occurrence of an interrupt event, it is determined whether to generate an interrupt request to the host system. This step of determining includes determining whether a predetermined interval of time has elapsed since the host system last processed an interrupt request or determining whether a predetermined number of interrupt events have occurred since the host system last processed an interrupt request. If the predetermined interval of time has elapsed or the predetermined number of events has occurred, respectively, the interrupt request from the adapter to the host system is generated.
    • 一种用于从主机系统请求中断来服务连接到主机系统的适配器和数据接口的方法和系统。 包括一个或多个数据单元的数据包在数据接口和主机系统之间传输。 主机系统包括主机存储器,其包括多个存储器插槽以存储在数据接口和主机系统之间传送的数据包。 确定何时传输数据导致发生中断事件。 当数据传输包括在数据接口和主机系统之间的数据信元的传送并且数据信元被定义为数据包的结尾时,发生中断事件。 响应于中断事件的发生,确定是否向主机系统生成中断请求。 该确定步骤包括确定从主机系统最后一次处理中断请求以来是否已经过去了预定的时间间隔,或者确定从主机系统最后一次处理中断请求以来是否发生了预定数量的中断事件。 如果预定的时间间隔已经过去或预定的事件数量分别发生,则从适配器向主机系统产生中断请求。