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11. 发明授权

US07633421B2 A/D converter 失效
标题翻译： A / D转换器
公开(公告)号：US07633421B2
公开(公告)日：2009-12-15
申请号：US12093252
申请日：2007-07-30
申请人： Shiro Dosho , Takashi Morie , Yusuke Tokunaga , Shiro Sakiyama
发明人： Shiro Dosho , Takashi Morie , Yusuke Tokunaga , Shiro Sakiyama
IPC分类号： H03M1/12
CPC分类号： H03M1/123 , H03M1/1215 , H03M1/56
摘要： An A/D converter includes: a plurality of A/D conversion circuits (10 a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.
摘要翻译： A / D转换器包括：多个A / D转换电路（10a，10b）; 输入选择部分（20），用于选择不执行A / D转换的A / D转换电路以提供通过采样保持输入信号获得的模拟量; 以及用于选择不执行A / D转换的A / D转换电路以输出从所选择的数字量获得的数字量的输出选择部分（30）。每个A / D转换电路包括：用于在多个模拟存储器元件（111）中顺序地存储所提供的模拟量的输入存储器部分（11）。具有用于将存储在模拟存储器元件中的模拟量转换为数字量的多个A / D转换元件的A / D转换部分（12）以及移位输出部分（13），具有从A / D转换元件接收数字量以保持数字量的多个寄存器（131），用于移位和输出保存在寄存器中的数字量。

12. 发明授权

US07388405B2 Signal transmission circuit 失效
标题翻译：信号传输电路
公开(公告)号：US07388405B2
公开(公告)日：2008-06-17
申请号：US11513239
申请日：2006-08-31
申请人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Makoto Hattori
发明人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Makoto Hattori
IPC分类号： H03K19/094 , H03K19/0175 , H03B1/00
CPC分类号： H03K19/018571 , H03F1/0261 , H03F3/505 , H03F2200/18 , H04L25/028
摘要： A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.
摘要翻译：源极跟随器的输出电压从低电平上升到预定电压所需的时间取决于偏置电压。因此，通过增加偏置电压来设定输出电压的收敛电压为高，可以降低上升到预定电压所需的时间。因此，当输入数据信号从低电平变为高电平时，被偏压使得输出电压的会聚值变为预定的Hi电压的第一源极跟随器，以及被偏置以便成为Hi电压之后的第二源极跟随器使用输入数据信号从低电平变为高电平时的一个时钟周期。两个来源追随者在适当的时机运行。

13. 发明申请

US20100225518A1 DIGITAL/ANALOG CONVERTER CIRCUIT 有权
标题翻译：数字/模拟转换器电路
公开(公告)号：US20100225518A1
公开(公告)日：2010-09-09
申请号：US12376400
申请日：2007-06-19
申请人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Kurumi Nakayama
发明人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Kurumi Nakayama
IPC分类号： H03M1/66
CPC分类号： G09G3/3685 , G09G3/3696 , G09G2310/027 , H03M1/76
摘要： A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).
摘要翻译：选择部（105）选择与数字数据（D-DATA）的数字值对应的，具有逐步变化的电压值的多个阶梯电压（SV1，SV2，SV3 ......等）中的阶梯电压。对于多个步进电压（SV1，SV2，SV3 ...）中的每一个，将不同的数字值分配给步进电压的不同步骤。放大器部分（106）放大由选择部分（105）选择的步进电压。输出部分（107）输出由放大器部分（106）放大的阶跃电压作为对应于数字数据（D-DATA）的数字值的时间周期的输出电压（Vout）。

14. 发明申请

US20070121761A1 Phase adjustment circuit 有权
标题翻译：相位调整电路
公开(公告)号：US20070121761A1
公开(公告)日：2007-05-31
申请号：US11514151
申请日：2006-09-01
申请人： Shiro Dosho , Shiro Sakiyama , Yusuke Tokunaga , Seiji Watanabe , Hiroshi Koshida
发明人： Shiro Dosho , Shiro Sakiyama , Yusuke Tokunaga , Seiji Watanabe , Hiroshi Koshida
IPC分类号： H04L27/22
CPC分类号： H03K5/13 , H03K5/15013 , H03K2005/00052 , H03K2005/00273
摘要： A phase adjustment circuit includes first to nth two-phase adjustment circuits. Each two-phase adjustment circuit includes a first logic circuit for performing logical sum of two input signals, a second logic circuit for performing logical product of the two input signals, a first delay circuit having a signal delay equal to that of the second logic circuit and configured to delay a signal output from the first logic circuit, and a second delay circuit having a signal delay equal to that of the first logic circuit and configured to delay a signal output from the second logic circuit. Two signals output from two of the two-phase adjustment circuits in a certain stage are input into one of the two-phase adjustment circuits in the next stage.
摘要翻译：相位调整电路包括第一至第二相位调整电路。每个两相调节电路包括用于执行两个输入信号的逻辑和的第一逻辑电路，用于执行两个输入信号的逻辑积的第二逻辑电路，具有等于第二逻辑电路的信号延迟的信号延迟的第一延迟电路并且被配置为延迟从第一逻辑电路输出的信号;以及第二延迟电路，其具有等于第一逻辑电路的信号延迟的信号延迟，并且被配置为延迟从第二逻辑电路输出的信号。在一定阶段从两相调节电路中输出的两个信号在下一级输入到两相调节电路之一。

15. 发明授权

US07936295B2 Digital/analog converter circuit 有权
标题翻译：数模转换电路
公开(公告)号：US07936295B2
公开(公告)日：2011-05-03
申请号：US12376400
申请日：2007-06-19
申请人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Kurumi Nakayama
发明人： Yusuke Tokunaga , Shiro Sakiyama , Shiro Dosho , Yasuyuki Doi , Kurumi Nakayama
IPC分类号： H03M1/78
CPC分类号： G09G3/3685 , G09G3/3696 , G09G2310/027 , H03M1/76
摘要： A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).
摘要翻译：选择部（105）选择与数字数据（D-DATA）的数字值对应的，具有逐步变化的电压值的多个阶梯电压（SV1，SV2，SV3 ......等）中的阶梯电压。对于多个步进电压（SV1，SV2，SV3 ...）中的每一个，将不同的数字值分配给步进电压的不同步骤。放大器部分（106）放大由选择部分（105）选择的步进电压。输出部分（107）输出由放大器部分（106）放大的阶跃电压作为对应于数字数据（D-DATA）的数字值的时间周期的输出电压（Vout）。

16. 发明授权

US07911369B2 Pipelined AD converter 有权
标题翻译：流水线AD转换器
公开(公告)号：US07911369B2
公开(公告)日：2011-03-22
申请号：US12600784
申请日：2008-08-21
申请人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
发明人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03M1/38
CPC分类号： H03M1/0678 , H03M1/0695 , H03M1/44
摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.
摘要翻译：流水线式AD转换器（1）包括多个转换级（11,11 ...）。在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2）以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。

17. 发明申请

US20100149010A1 PIPELINED AD CONVERTER 有权
标题翻译：管路AD转换器
公开(公告)号：US20100149010A1
公开(公告)日：2010-06-17
申请号：US12600784
申请日：2008-08-21
申请人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
发明人： Takashi Morie , Kazuo Matsukawa , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03M1/38 , H03M1/00
CPC分类号： H03M1/0678 , H03M1/0695 , H03M1/44
摘要： A pipelined AD converter (1) includes a plurality of conversion stages (11, 11, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit (101) converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit (102) converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit (103) has: a capacitor section (C1, C2) for sampling the input voltage; and an amplifier section (104) for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section (104) includes a plurality of op-amps (amp1, amp1, . . . ) having the same configuration and connected in parallel with each other.
摘要翻译：流水线式AD转换器（1）包括多个转换级（11,11 ...）。在每个转换级中，模数转换电路（101）将来自前级的输入电压（Vin）转换为数字代码（Dout）。数模转换电路（102）将由模数转换电路获得的数字代码转换为中间电压（Vda）。充电操作电路（103）具有用于对输入电压进行采样的电容器部（C1，C2）以及用于放大由电容器部分采样的输入电压和由数模转换电路获得的中间电压的混合电压的放大器部分（104）。放大器部分（104）包括具有相同配置并且彼此并联的多个运算放大器（amp1，amp1 ...）。

18. 发明申请

US20080315933A1 PULSE SYNTHESIS CIRCUIT 有权
标题翻译：脉冲合成电路
公开(公告)号：US20080315933A1
公开(公告)日：2008-12-25
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K3/00
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

19. 发明授权

US08212624B2 Reference frequency generation circuit, semiconductor integrated circuit, and electronic device 有权
标题翻译：参考频率发生电路，半导体集成电路和电子设备
公开(公告)号：US08212624B2
公开(公告)日：2012-07-03
申请号：US13022029
申请日：2011-02-07
申请人： Yusuke Tokunaga , Shiro Sakiyama , Akinori Matsumoto , Shiro Dosho
发明人： Yusuke Tokunaga , Shiro Sakiyama , Akinori Matsumoto , Shiro Dosho
IPC分类号： H02K3/26
CPC分类号： H03K4/501
摘要： An oscillator circuit increases and reduces signal levels of first and second oscillation signals in a complementary manner in response to a transition of a signal level of a reference clock. An oscillation control circuit compares each of the signal levels of the first and second oscillation signals to a comparison voltage, and causes the signal level of the reference clock to transition according to results of the comparison. A reference control circuit increases or reduces the comparison voltage so that a difference between a signal level of an intermediate signal which is proportional to respective swings of the first and second oscillation signals and a reference voltage is reduced.
摘要翻译：响应于参考时钟的信号电平的转变，振荡器电路以互补的方式增加并降低第一和第二振荡信号的信号电平。振荡控制电路将第一和第二振荡信号的每个信号电平与比较电压进行比较，并根据比较结果使参考时钟的信号电平转变。参考控制电路增加或减小比较电压，使得与第一和第二振荡信号的相应摆动成比例的中间信号的信号电平与参考电压之间的差减小。

20. 发明授权

US08130608B2 Coupled ring oscillator and method for initializing the same 有权
标题翻译：耦合环形振荡器及其初始化方法
公开(公告)号：US08130608B2
公开(公告)日：2012-03-06
申请号：US12967498
申请日：2010-12-14
申请人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Shiro Dosho , Yusuke Tokunaga , Takashi Morie
IPC分类号： G11B7/00 , H03K3/03
CPC分类号： H03K3/0315 , H03K2005/00052
摘要： In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.
摘要翻译：在包括q个环形振荡器的耦合环形振荡器中，每个环形振荡器包括连接在一起以形成环形的p个反相器电路，以及包括（p×q）个相位耦合电路的相位耦合环，每个相位耦合电路被配置为耦合p的一个的输出 q环振荡器中的一个的逆变器电路以预定的相位关系连接到另一个q个环形振荡器的p个反相器电路之一的输出，并且连接在一起以形成环形，用于至少一个组每个q环振荡器中的p个反相器电路中的一个的上升，属于至少一个组的q个反相器电路的输出彼此相位固定，使q个环形振荡器在同相中振荡固定状态，然后将q个逆变器电路的输出从同相固定状态解除。

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