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11. 发明申请

US20180326744A1 IMAGE RECORDING DEVICE AND IMAGE RECORDING METHOD 审中-公开
公开(公告)号：US20180326744A1
公开(公告)日：2018-11-15
申请号：US16045003
申请日：2018-07-25
申请人： Ichiro SAWAMURA , Yoshihiko HOTTA , Kazuyuki UETAKE , Tomomi ISHIMI , Yasuroh YOKOTA
发明人： Ichiro SAWAMURA , Yoshihiko HOTTA , Kazuyuki UETAKE , Tomomi ISHIMI , Yasuroh YOKOTA
IPC分类号： B41J2/455 , B41J2/475 , B41J2/47 , B41M5/30
CPC分类号： B41J2/455 , B41J2/447 , B41J2/46 , B41J2/473 , B41J2/4753 , B41M5/305 , G02B6/3839 , H01S5/02415 , H01S5/042
摘要： An image recording device includes a laser irradiation device that emits laser lights output from a plurality of laser light emitting elements to different positions in a predetermined direction; and an image recording unit that controls the laser irradiation device to irradiate a recording object moving relative to the laser irradiation device in a direction different from the predetermined direction with laser so as to heat the object, form image dots, and record an image. The image recording unit controls the laser irradiation device, conducts recording such that at least one of the image dots, recorded alongside at different positions in a direction perpendicular to a relative moving direction of the object, is shifted relative to other ones of the image dots in the relative moving direction, and records a solid image on the object such that the image dot is partially overlapped with all adjacent image dots.

12. 发明申请

US20170225489A1 RECORDING METHOD AND RECORDING DEVICE 审中-公开
公开(公告)号：US20170225489A1
公开(公告)日：2017-08-10
申请号：US15424728
申请日：2017-02-03
申请人： Kazuyuki UETAKE , Yoshihiko HOTTA , Ichiro SAWAMURA , Tomomi ISHIMI , Yasuroh YOKOTA
发明人： Kazuyuki UETAKE , Yoshihiko HOTTA , Ichiro SAWAMURA , Tomomi ISHIMI , Yasuroh YOKOTA
IPC分类号： B41J2/46 , B41J2/47
CPC分类号： B41J2/46 , B41J2/47
摘要： Recording method including: emitting laser-light from optical-fiber-array to record image of writing-units with moving recording target and the optical-fiber-array relatively using recording device including laser-light-emitting-elements and emitting unit including the optical-fiber-array, where optical fibers to guide laser-light emitted from the laser-light-emitting-elements are aligned, wherein diagonal line A′C is longer than B in the image formed by overlapping or adjoining at least part of the writing-units in main-scanning direction, where B is length of ½ line width of the writing-unit in main-scanning direction, A is center of edge of the writing-unit in sub-scanning direction, A′ is position proceeded from A towards inner-side of the writing-unit by B, line LL′ is drawn to include A and be orthogonal to the writing-unit, diagonal-line is drawn with A as starting point and to have angle of 45° with line LL′, and C is intersection between the diagonal-line and the writing-unit.

13. 发明申请

US20110314323A1 SEMICONDUCTOR DEVICE AND DATA PROCESSOR 有权
标题翻译：半导体器件和数据处理器
公开(公告)号：US20110314323A1
公开(公告)日：2011-12-22
申请号：US13220747
申请日：2011-08-30
申请人： Yoshihiko HOTTA , Seiichi SAITO , Hiroyuki HAMASAKI , Hirotaka HARA , Itaru NONOMURA
发明人： Yoshihiko HOTTA , Seiichi SAITO , Hiroyuki HAMASAKI , Hirotaka HARA , Itaru NONOMURA
IPC分类号： G06F1/12
CPC分类号： G06F1/3253 , G06F1/3237 , Y02D10/128 , Y02D10/151
摘要： To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
摘要翻译：提高从高速电路块访问低速电路块的速度，而不会显着增加功耗。在具有总线控制器的数据处理器中，总线控制器执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路，提供定时控制电路在外围电路和总线控制器之间，并且总线控制器响应于来自外围电路的读取指令而导致定时控制电路将周边电路保持的数据与高速的周期同步地传送到总线控制器速度时钟信号，使定时控制电路响应于指向外围电路的写指令而启动，与高速时钟信号的周期同步地写入外围电路，并且与低速时钟信号的周期。

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