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11. 发明授权

US06421291B1 Semiconductor memory device having high data input/output frequency and capable of efficiently testing circuit associated with data input/output 失效
标题翻译：具有高数据输入/输出频率并能够有效测试与数据输入/输出相关的电路的半导体存储器件
公开(公告)号：US06421291B1
公开(公告)日：2002-07-16
申请号：US09510532
申请日：2000-02-22
申请人： Naoya Watanabe , Yoshikazu Morooka
发明人： Naoya Watanabe , Yoshikazu Morooka
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/1006 , G11C29/02
摘要： A data input/output circuit includes an S/P data conversion circuit which converts serial data input to a data terminal into a parallel data and transmits the parallel data to write data lines, a P/S data conversion circuit which converts parallel data on read data lines to serial data and outputs the serial data to the data terminal, and an input/output test circuit placed between the write data lines and the read data lines. The input/output test circuit responds to an input/output test signal to directly transfer data on the write data lines respectively to the read data lines without passing them through a memory cell array.
摘要翻译：数据输入/输出电路包括将输入到数据终端的串行数据转换为并行数据并将并行数据发送到写入数据线的S / P数据转换电路，将读取的并行数据转换成P / S数据转换电路数据线连接到串行数据，并将串行数据输出到数据终端，以及输入/输出测试电路，位于写数据线和读数据线之间。输入/输出测试电路响应于输入/输出测试信号，以将数据线上的数据直接传送到读取的数据线，而不会将它们通过存储单元阵列。

12. 发明申请

US20100257324A1 INTERFACE CIRCUIT 审中-公开
标题翻译：接口电路
公开(公告)号：US20100257324A1
公开(公告)日：2010-10-07
申请号：US12751810
申请日：2010-03-31
申请人： Tokuya Osawa , Masaru Haraguchi , Yoshikazu Morooka , Hiroshi Kinoshita
发明人： Tokuya Osawa , Masaru Haraguchi , Yoshikazu Morooka , Hiroshi Kinoshita
IPC分类号： G06F12/00
CPC分类号： G11C8/08 , G11C7/1066
摘要： A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.
摘要翻译：可变延迟线接收并延迟从数据源侧与传送数据同步预定周期的数据选通信号，并将延迟数据选通信号和非延迟数据选通信号提供给检测器。当非延迟数据选通信号从L电平上升到H电平时，当延迟的数据选通信号为L电平时，检测器确定前导码周期结束并传送有效数据。根据检测结果，接口电路单元接收传送数据并初始化接收地址。当后同步码结束时，数据选通信号变为高阻态。数据选通信号的变化可以避免毛刺噪声的影响，可以快速准确地执行数据传送。

13. 发明申请

US20080031079A1 Interface circuit 失效
标题翻译：接口电路
公开(公告)号：US20080031079A1
公开(公告)日：2008-02-07
申请号：US11882117
申请日：2007-07-30
申请人： Tokuya Osawa , Masaru Haraguchi , Yoshikazu Morooka , Hiroshi Kinoshita
发明人： Tokuya Osawa , Masaru Haraguchi , Yoshikazu Morooka , Hiroshi Kinoshita
IPC分类号： G11C8/18
CPC分类号： G11C8/08 , G11C7/1066
摘要： A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.
摘要翻译：可变延迟线接收并延迟从数据源侧与传送数据同步预定周期的数据选通信号，并将延迟数据选通信号和非延迟数据选通信号提供给检测器。当非延迟数据选通信号从L电平上升到H电平时，当延迟的数据选通信号为L电平时，检测器确定前导码周期结束并传送有效数据。根据检测结果，接口电路单元接收传送数据并初始化接收地址。当后同步码结束时，数据选通信号变为高阻态。数据选通信号的变化可以避免毛刺噪声的影响，可以快速准确地执行数据传送。

14. 发明授权

US5404329A Boosting circuit improved to operate in a wider range of power supply voltage, and a semiconductor memory and a semiconductor integrated circuit device using the same 失效
标题翻译：升压电路改进以在更宽的电源电压范围内工作，以及使用其的半导体存储器和半导体集成电路器件
公开(公告)号：US5404329A
公开(公告)日：1995-04-04
申请号：US92109
申请日：1993-07-16
申请人： Tadato Yamagata , Yoshikazu Morooka
发明人： Tadato Yamagata , Yoshikazu Morooka
IPC分类号： G11C11/413 , G11C8/08 , G11C11/407 , G11C11/409 , H01L27/02 , H02M3/07 , H03K5/02 , H03K19/017 , H03K4/58
CPC分类号： H03K19/01735 , G11C8/08 , H01L27/0218 , H02M3/07
摘要： A boosting circuit is provided applicable in various semiconductor integrated circuits such as a word line boosting circuit in a semiconductor memory. Because a backgate electrode of a PMOS transistor connected between power supply potential and an output node is connected to the output node, the output node is precharged to the Vcc level during a boosting term. Therefore, the boosting condition by a MOS capacitor is alleviated in comparison with a conventional boosting circuit. Proper boosting operation can be carried out even at a lower level of a supplied power supply voltage. Therefore, operable margin of power supply voltage is enlarged.
摘要翻译：升压电路适用于半导体存储器中诸如字线升压电路的各种半导体集成电路。因为连接在电源电位和输出节点之间的PMOS晶体管的背栅电极连接到输出节点，所以在升压期间输出节点被预充电到Vcc电平。因此，与传统的升压电路相比，MOS电容器的升压状态得到缓解。即使在所提供的电源电压的较低水平下也可以进行适当的升压操作。因此，电源电压的可操作余量被扩大。

15. 发明授权

US06304502B1 Semiconductor memory device connected to memory controller and memory system employing the same 失效
标题翻译：连接到存储器控制器的半导体存储器件和采用该存储器的存储器系统
公开(公告)号：US06304502B1
公开(公告)日：2001-10-16
申请号：US09215227
申请日：1998-12-18
申请人： Naoya Watanabe , Yoshikazu Morooka
发明人： Naoya Watanabe , Yoshikazu Morooka
IPC分类号： G11C700
CPC分类号： G11C29/76 , G11C29/14 , G11C29/44
摘要： Each SLDRAM tests a built in memory section in response to a test execution command supplied from a memory controller and sends a defective address to memory controller. Memory controller stores the defective address of each SLDRAM and accesses only to a normal address and does not access to the defective address. The rate of memory capacity decrease of a main memory can be suppressed compared with a conventional technique where an SLDRAM having a defective address is not accessed.
摘要翻译：每个SLDRAM都会根据从存储器控制器提供的测试执行命令来测试内置存储器部分，并将缺陷地址发送到存储器控制器。存储器控制器存储每个SLDRAM的缺陷地址，并仅访问正常地址，并且不访问有缺陷的地址。与不存在具有不良地址的SLDRAM的传统技术相比，可以抑制主存储器的存储容量下降的速率。

16. 发明授权

US5469402A Buffer circuit of a semiconductor memory device 失效
标题翻译：半导体存储器件的缓冲电路
公开(公告)号：US5469402A
公开(公告)日：1995-11-21
申请号：US305632
申请日：1994-09-14
申请人： Tadaaki Yamauchi , Kei Hamade , Yoshikazu Morooka
发明人： Tadaaki Yamauchi , Kei Hamade , Yoshikazu Morooka
IPC分类号： G11C11/413 , G11C8/06 , G11C8/18 , G11C11/408
CPC分类号： G11C8/06 , G11C8/18
摘要： An internal address signal is outputted quickly by connecting nMOS transistors in series to inverters forming a latching circuit of a row address buffer circuit, applying an external row address signal to the gate of a nMOS transistor, applying a delayed activation signal .phi.2 to the gate of the nMOS transistors, grounding the gate of the nMOS transistor, triggering nMOS transistors into complete conduction by the delayed activation signal .phi.2 to reduce the ON resistance. A column address buffer circuit receives a ZCAS circuit by an NOR gate, and an external column address signal by an NAND gate during standby, to prevent a flow of a through current.
摘要翻译：通过将nMOS晶体管串联连接到形成行地址缓冲电路的锁存电路的反相器，快速地输出内部地址信号，向nMOS晶体管的栅极施加外部行地址信号，将延迟的激活信号phi2施加到栅极 nMOS晶体管的栅极接地，将nMOS晶体管触发通过延迟的激活信号phi2完全导通，以降低导通电阻。列地址缓冲电路通过NOR门接收ZCAS电路，在待机期间通过NAND门接收外部列地址信号，以防止通过电流的流动。

17. 发明授权

US4734889A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US4734889A
公开(公告)日：1988-03-29
申请号：US837359
申请日：1986-03-06
申请人： Koichiro Mashiko , Yoshikazu Morooka , Tadato Yamagata , Yuto Ikeda
发明人： Koichiro Mashiko , Yoshikazu Morooka , Tadato Yamagata , Yuto Ikeda
IPC分类号： G11C11/408 , G11C29/00 , G11C13/00 , G11C11/40
CPC分类号： G11C29/84
摘要： A spare Y decoder is provided with MOS transistors 14 and 20 for charge on both sides of a parasitic resistor 19. As a result, nodes N1 and N2 are rapidly charged by the MOS transistors 20 and 14 for charge, respectively.
摘要翻译：备用Y解码器设置有MOS晶体管14和20，用于在寄生电阻器19的两侧充电。结果，节点N1和N2分别被MOS晶体管20和14快速充电。

18. 发明授权

US6160434A Ninety-degree phase shifter 失效
标题翻译：九十度移相器
公开(公告)号：US6160434A
公开(公告)日：2000-12-12
申请号：US177379
申请日：1998-10-23
申请人： Tsutomu Yoshimura , Yasunobu Nakase , Yoshikazu Morooka , Naoya Watanabe
发明人： Tsutomu Yoshimura , Yasunobu Nakase , Yoshikazu Morooka , Naoya Watanabe
IPC分类号： H03K5/00 , H03K5/13
CPC分类号： H03K5/133 , H03K2005/00039 , H03K2005/00286
摘要： Transistors (MP1 and MP2) supply a current (I.sub.0) for nodes (K and L), respectively. Transistors (MN10 and MN11) draw the same current from nodes (K and L), respectively. A parallel connection of serial connections (N1 and N2) draws a current (I.sub.1) from the node (K) only when an exclusive OR of clocks (S1 and S2) is "H". On the other hand, a parallel connection of serial connections (N3 and N4) draws a current (I.sub.1) from the node (L) only when the exclusive OR of clocks (S1 and S2) is "L". When the current (I.sub.1) is drawn from the node (K), the current (I.sub.1) flows out from the node (L) and when the current (I.sub.1) is drawn from the node (L), the current (I.sub.1) flows into the node (L). In the serial connections (N1 to N4), each of the clocks (S1 and S2) and their inverted signals (S1B and S2B) is applied to one of the gates of the transistors (MN1 to MN8) and therefore a uniform input load is obtained. With this configuration provided is a 90-degree phase shifter which achieves the uniform input load to improve a phase offset.
摘要翻译：晶体管（MP1和MP2）分别为节点（K和L）提供电流（I0）。晶体管（MN10和MN11）分别从节点（K和L）绘出相同的电流。串行连接（N1和N2）的并联连接仅在时钟（S1和S2）的异或“为”H“时从节点（K）抽出电流（I1）。另一方面，仅当时钟（S1和S2）的异或为“L”时，串行连接（N3和N4）的并联连接从节点（L）抽出电流（I1）。当从节点（K）抽出电流（I1）时，电流（I1）从节点（L）流出，当电流（I1）从节点（L）抽出时，电流（I1）流进入节点（L）。在串行连接（N1〜N4）中，每个时钟（S1和S2）及其反相信号（S1B和S2B）被施加到晶体管（MN1至MN8）的一个栅极，因此均匀的输入负载获得。所提供的这种配置是实现均匀输入负载以提高相位偏移的90度移相器。

19. 发明授权

US6101151A Synchronous semiconductor memory device employing temporary data output stop scheme 失效
标题翻译：采用临时数据输出停止方案的同步半导体存储器件
公开(公告)号：US6101151A
公开(公告)日：2000-08-08
申请号：US196245
申请日：1998-11-20
申请人： Naoya Watanabe , Yoshikazu Morooka , Tsutomu Yoshimura , Yasunobu Nakase
发明人： Naoya Watanabe , Yoshikazu Morooka , Tsutomu Yoshimura , Yasunobu Nakase
IPC分类号： G11C11/413 , G11C7/00 , G11C7/10 , G11C7/22 , G11C11/407 , G11C11/409 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1072
摘要： In a synchronous semiconductor memory device in which an internal clock signal from an internal timing clock signal generating circuit is branched in the form of a tree by driver circuits and applied to output buffers and data are output in synchronization with the internal clock signal, the driver circuit of the first stage is constituted by an NAND gate and an inverter. When output is to be temporarily stopped, an enabling signal is set to "L" level, so that the NAND gate is closed, output of the clock signal to each driver circuit is stopped, and thus power consumption is reduced.
摘要翻译：在同步半导体存储器件中，来自内部定时时钟信号产生电路的内部时钟信号以树形式被驱动电路分支并且被施加到输出缓冲器和数据与内部时钟信号同步输出，第一级的电路由NAND门和反相器构成。当暂时停止输出时，使能信号被设置为“L”电平，使得与非门关闭，从而停止对每个驱动电路的时钟信号的输出，从而降低功耗。

20. 发明授权

US5995435A Semiconductor memory device having controllable supplying capability of internal voltage 失效
标题翻译：具有可控的内部电压供应能力的半导体存储器件
公开(公告)号：US5995435A
公开(公告)日：1999-11-30
申请号：US137707
申请日：1998-08-21
申请人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
发明人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
IPC分类号： G11C11/407 , G11C5/14 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C13/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4074 , G11C5/146
摘要： When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.
摘要翻译：当外部+ E，ovs RAS + EE和外部+ E，ovs CAS + EE输入到RAS缓冲区，CAS缓冲区，内部+ E，ovs RAS + EE和内部+ E，ovs CAS + EE 生成。内部+ E，ovs RAS + EE输入到时钟发生电路和CBR模式确定电路，内部+ E，ovs CAS + EE输入到CBR模式确定电路。时钟发生电路在内部+ E，RAS + EE输入时向第一和第二WL泵输出泵时钟，第一WL泵为Vpp电源供电。如果+ E，则在+ E之前输入ovs CAS + EE，在刷新操作期间输入ovs RAS + EE，CBR模式确定电路将CBR模式信号输入到与第一WL泵一起向Vpp电源提供电荷的第二WL泵当泵时钟和CBR模式信号被输入时。

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