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11. 发明授权

US06445709B1 Method and apparatus for finding a match entry using receive port number embedded in the port vector 有权
标题翻译：使用嵌入在端口向量中的接收端口号来找到匹配条目的方法和装置
公开(公告)号：US06445709B1
公开(公告)日：2002-09-03
申请号：US09311367
申请日：1999-05-13
申请人： John M. Chiang
发明人： John M. Chiang
IPC分类号： H04L1256
CPC分类号： H04L49/354 , H04L12/4645 , H04L12/467 , H04L49/205 , H04L49/3009 , H04L49/3027 , H04L49/351
摘要： A network switch configured for switching data packets across multiple ports uses an address table to generated frame forwarding information. The switch receives frame information including a source address and destination address along with a virtual local area network (VLAN) ID, if applicable. A decision-making engine searches a network address table to “learn” Medium Access Control (MAC) addresses without having to store receive port numbers by embedding the receive port number in the stored port vector fields.
摘要翻译：配置为跨多个端口切换数据包的网络交换机使用地址表来生成帧转发信息。如果适用，交换机接收包括源地址和目的地址以及虚拟局域网（VLAN）ID的帧信息。决策引擎搜索网络地址表以“学习”媒体访问控制（MAC）地址，而不必通过将接收端口号嵌入存储的端口向量域中来存储接收端口号。

12. 发明授权

US08913895B1 Method and apparatus for controlling timing of a transmission signal from a network termination device 有权
标题翻译：用于控制来自网络终端设备的传输信号的定时的方法和装置
公开(公告)号：US08913895B1
公开(公告)日：2014-12-16
申请号：US13523610
申请日：2012-06-14
申请人： John M. Chiang , Cesar A. Johnston
发明人： John M. Chiang , Cesar A. Johnston
IPC分类号： H04B10/40
CPC分类号： H04J3/0682 , H04J3/0694 , H04Q11/0067 , H04Q2011/0079
摘要： In a method for controlling timing of a transmission signal from a network termination device having a receiver and a transmitter, a signal is received at the receiver of the network termination device, the signal having been transmitted in accordance with a predetermined bit rate. A core clock signal for the receiver is determined based on the predetermined bit rate at which the signal was transmitted, and the core clock signal is communicated to the transmitter of the network termination device. At the transmitter of the network termination device, a phase adjusted clock signal is generated, and the phase adjusted clock signal is set as the transmitter clock signal. The transmitter clock signal is offset from the core clock signal, and the transmission signal is transmitted from the transmitter of the network termination device based on the transmitter clock signal.
摘要翻译：在用于控制来自具有接收机和发射机的网络终端装置的发送信号的定时的方法中，在网络终端装置的接收机处接收信号，该信号已经根据预定的比特率被发送。基于发送信号的预定比特率来确定用于接收机的核心时钟信号，并且将核心时钟信号传送到网络终端设备的发射机。在网络终端装置的发射机处，生成相位调整后的时钟信号，将相位调整后的时钟信号设定为发射机时钟信号。发射机时钟信号与核心时钟信号偏移，并且发射信号基于发射机时钟信号从网络终端装置的发射机发射。

13. 发明授权

US08718087B1 Processing architecture for passive optical network 失效
标题翻译：无源光网络处理架构
公开(公告)号：US08718087B1
公开(公告)日：2014-05-06
申请号：US11877379
申请日：2007-10-23
申请人： Cesar A. Johnston , John M. Chiang
发明人： Cesar A. Johnston , John M. Chiang
IPC分类号： H04L12/66
CPC分类号： H04L12/12 , Y02D50/40
摘要： In a network termination device integrated circuit in a point-to-multipoint network, a receiver receives a downstream transmission from a line termination unit within the point-to-multipoint network, a transmitter transmits an upstream transmission to the line termination unit within the point-to-multipoint network, and an internal processor operatively coupled to the receiver processes sub-fields within the overhead field of the downstream transmission. The internal processor is also operatively coupled to the transmitter to assemble the overhead field of the upstream transmission. The downstream transmission is an downstream transmission convergence frame format having an overhead field and a payload field, and the upstream transmission is an upstream transmission convergence frame format having an overhead field and a payload field.
摘要翻译：在点对多点网络中的网络终端设备集成电路中，接收器从点对多点网络中的线路终端单元接收下行传输，发射机将该上行传输发送到该点到多点网络内的线路终端单元以及可操作地耦合到所述接收机的内部处理器处理所述下行传输的开销字段内的子域。内部处理器还可操作地耦合到发射机以组合上行传输的开销字段。下行传输是具有开销字段和有效载荷字段的下行传输会聚帧格式，上行传输是具有开销字段和有效载荷字段的上行传输会聚帧格式。

14. 发明授权

US08208815B1 Bit accurate upstream burst transmission phase method for reducing burst data arrival variation 有权
标题翻译：用于减少突发数据到达变化的位精确上行脉冲串传输相位方法
公开(公告)号：US08208815B1
公开(公告)日：2012-06-26
申请号：US11948575
申请日：2007-11-30
申请人： John M. Chiang , Cesar A. Johnston
发明人： John M. Chiang , Cesar A. Johnston
IPC分类号： H04B10/00
CPC分类号： H04J3/0682 , H04J3/0694 , H04Q11/0067 , H04Q2011/0079
摘要： In a method for controlling timing of an upstream from an optical network termination device to an optical line termination device, a downstream transmission is analyzed to determine a core clock rate for the termination device. The core clock signal is then used to determine a transmitter clock signal to be used for upstream transmission, where the transmitter clock signal is offset from the core clock signal. The offset transmitter clock signal may be determined in the receiver or in the transmitter of the termination device and by a delay lock loop or by a clock data recovery/generator circuitry. For example, the transmitter clock signal may be taken from a plurality of phase adjusted clock offset signals created by the clock data recovery/generator circuitry during identification of the core clock signal.
摘要翻译：在用于控制从光网络终端设备到光线路终端设备的上游的定时的方法中，分析下行传输以确定终端设备的核心时钟速率。核心时钟信号然后用于确定要用于上行传输的发射机时钟信号，其中发射机时钟信号偏离核心时钟信号。偏移发射机时钟信号可以在终端设备的接收机或发射机中以及延迟锁定环路或时钟数据恢复/发生器电路中确定。例如，在核心时钟信号的识别期间，发射机时钟信号可以取自由时钟数据恢复/发生器电路产生的多个相位调整的时钟偏移信号。

15. 发明授权

US07983308B1 Method and apparatus for data frame synchronization 有权
标题翻译：用于数据帧同步的方法和装置
公开(公告)号：US07983308B1
公开(公告)日：2011-07-19
申请号：US11939513
申请日：2007-11-13
申请人： Cesar A. Johnston , John M. Chiang
发明人： Cesar A. Johnston , John M. Chiang
IPC分类号： H04J3/06 , H04L7/00 , H04B10/00
CPC分类号： H04J3/0608 , H04L7/033 , H04Q11/0067 , H04Q2011/0083
摘要： A circuit to synchronize with a data transmission includes a comparator to read a set of data within a serialized data transmission, compare the set of data to a predetermined data pattern and output a comparison result. For a serialized data transmission, the comparator receives the serialized transmission and a shift register serially coupled to the comparator to hold the data pattern. A synchronization detector receives a comparison hit vector based on the comparison result from the comparator and aligns a boundary of a data frame according to the comparison hit vector if the comparison hit vector indicates a match between the data pattern in the set of data and the predetermined data pattern. For a deserialized data transmission, each stage of a multistage shift register read a set of data from the deserialized data transmission and selectively outputs the set of data to a comparator which compares each set to a predetermined data pattern and output a comparison result. A synchronization detector receives the comparison result from the comparator and aligns a boundary of a data frame according to the comparison result if the comparison result indicates a match between a data pattern sub-set within a combined data pattern and the predetermined data pattern, where the sets of deserialized data comprise the combined data pattern.
摘要翻译：与数据传输同步的电路包括比较器，用于读取串行化数据传输中的一组数据，将该组数据与预定数据模式进行比较并输出比较结果。对于串行数据传输，比较器接收串行化传输和串行耦合到比较器的移位寄存器以保持数据模式。同步检测器基于来自比较器的比较结果接收比较命中矢量，如果比较命中矢量指示数据组中的数据模式与预定的数据模式之间的匹配，则根据比较命中向量对齐数据帧的边界数据模式。对于反序列化数据传输，多级移位寄存器的每一级从反序列化数据传输中读取一组数据，并选择性地将该组数据输出到比较器，该比较器将每组与预定数据模式进行比较并输出比较结果。如果比较结果指示组合数据模式中的数据模式子集与预定数据模式之间的匹配，则同步检测器从比较器接收比较结果并根据比较结果对准数据帧的边界，其中反序列化数据集包括组合数据模式。

16. 发明授权

US07970962B2 Method and apparatus utilizing a tail bus to solve back-to-back data burst problems 有权
标题翻译：利用尾巴解决背对背数据突发问题的方法和装置
公开(公告)号：US07970962B2
公开(公告)日：2011-06-28
申请号：US10269989
申请日：2002-10-15
申请人： Ngok Ying Chu , John M. Chiang
发明人： Ngok Ying Chu , John M. Chiang
IPC分类号： G06F13/00 , G06F13/12 , G06F15/173 , G06F15/16 , G01R31/08 , H04B7/216 , H04L12/28 , H04J3/16 , G10H7/04 , G10H1/00
CPC分类号： H04L12/4013 , G06F13/28 , G06F13/4004 , H04L12/40032
摘要： A network device includes a port and a bus transmission calculation module. The port is connected to the network device to receive a data burst. The bus transmission calculation module connects to the port for calculating a first number of bytes to be transmitted from a first bus and a second number of bytes to be transmitted from a second bus. The first and second bus connect to the network device and transfer data from the network device.
摘要翻译：网络设备包括端口和总线传输计算模块。该端口连接到网络设备以接收数据突发。总线传输计算模块连接到端口，用于计算要从第一总线发送的第一数量的字节和要从第二总线发送的第二数量的字节。第一和第二总线连接到网络设备并从网络设备传输数据。

17. 发明授权

US09178713B1 Optical line termination in a passive optical network 有权
标题翻译：无源光网络中的光线路终端
公开(公告)号：US09178713B1
公开(公告)日：2015-11-03
申请号：US11937396
申请日：2007-11-08
申请人： Cesar A. Johnston , John M. Chiang
发明人： Cesar A. Johnston , John M. Chiang
IPC分类号： H04L12/28 , H04L7/00 , H04J3/16 , H04J14/00
CPC分类号： H04L12/2898 , H04J3/1652 , H04L7/0075 , H04L12/2861 , H04Q11/0067 , H04Q2011/0064
摘要： In a line termination unit integrated circuit in a point-to-multipoint network, a receiver receives an upstream transmission from a network termination unit within the point-to-multipoint network, a transmitter transmits a downstream transmission to a network termination unit within the point-to-multipoint network, and an internal processor operatively coupled to the receiver processes sub-fields within the overhead field of the upstream transmission. The internal processor is also operatively coupled to the transmitter to assemble the overhead field of the downstream transmission. The upstream transmission is an upstream transmission convergence frame format having an overhead field and a payload field, and the downstream transmission is a downstream transmission convergence frame format having an overhead field and a payload field.
摘要翻译：在点对多点网络中的线路终端单元集成电路中，接收机从点对多点网络中的网络终端单元接收上行传输，发射机向所述点到多点网络内的网络终端单元发送下行传输以及可操作地耦合到所述接收机的内部处理器处理所述上行传输的开销字段内的子域。内部处理器也可操作地耦合到发射器以组装下游传输的开销字段。上行传输是具有开销字段和有效载荷字段的上行传输会聚帧格式，下行传输是具有开销字段和有效载荷字段的下行传输会聚帧格式。

18. 发明授权

US08582707B2 Programmable universal asynchronous receiver/transmitter (UART) based on reference frequency 失效
标题翻译：基于参考频率的可编程通用异步收发器（UART）
公开(公告)号：US08582707B2
公开(公告)日：2013-11-12
申请号：US12877823
申请日：2010-09-08
申请人： John M. Chiang
发明人： John M. Chiang
IPC分类号： H04L7/00
CPC分类号： H04L7/08 , H04L7/10 , H04L25/0262
摘要： In one embodiment, a method includes determining pre-calculated information. The pre-calculated information is used to determine a counter pattern for a reference clock. The counter pattern include, for at least one data bit, a number of reference clock cycles of the reference clock that is determined based on a frequency of the reference clock and a data rate of a serial data stream. The serial data stream is sampled to read a plurality of data bits based on the counter pattern. A data bit is sampled based on the number of reference clock cycles associated with the data bit.
摘要翻译：在一个实施例中，一种方法包括确定预先计算的信息。预先计算的信息用于确定参考时钟的计数器模式。对于至少一个数据位，计数器模式包括基于参考时钟的频率和串行数据流的数据速率确定的参考时钟的参考时钟周期的数量。对串行数据流进行采样，以便根据计数器模式读取多个数据位。基于与数据位相关联的参考时钟周期的数量对数据位进行采样。

19. 发明授权

US08326938B1 Packet buffer apparatus and method 有权
标题翻译：分组缓冲装置和方法
公开(公告)号：US08326938B1
公开(公告)日：2012-12-04
申请号：US13228936
申请日：2011-09-09
申请人： John M. Chiang , Cesar A. Johnston
发明人： John M. Chiang , Cesar A. Johnston
IPC分类号： G06F15/167
CPC分类号： H01M4/92 , H01M4/925 , H01M4/926 , H01M2008/1095
摘要： An apparatus including a first memory, a second memory, and a direct memory access engine. The first memory stores one or more packet descriptors. The second memory stores one or more packets for transmission via a communication link. The direct memory access engine is configured to i) determine when the one or more packet descriptors have been written, by a host, to the first memory, ii) read the one or more packet descriptors from the first memory in response to determining that the one or more packet descriptors have been written to the first memory by the host, iii) determine, using the one or more packet descriptors, one or more respective locations of one or more packets in a host memory, and iv) initiate a direct memory access transfer of the one or more packets from the one or more respective locations in the host memory to the second memory.
摘要翻译：一种包括第一存储器，第二存储器和直接存储器存取引擎的装置。第一存储器存储一个或多个分组描述符。第二存储器存储用于经由通信链路传输的一个或多个分组。直接存储器访问引擎被配置为i）确定一个或多个分组描述符何时被主机写入到第一存储器，ii）响应于确定所述第一存储器读取所述一个或多个分组描述符，一个或多个分组描述符已被主机写入第一存储器，iii）使用一个或多个分组描述符确定主机存储器中的一个或多个分组的一个或多个相应位置，以及iv）发起直接存储器将一个或多个分组从主机存储器中的一个或多个相应位置的访问传输到第二存储器。

20. 发明授权

US07818389B1 Packet buffer apparatus and method 有权
标题翻译：分组缓冲装置和方法
公开(公告)号：US07818389B1
公开(公告)日：2010-10-19
申请号：US11948753
申请日：2007-11-30
申请人： John M. Chiang , Cesar A. Johnston
发明人： John M. Chiang , Cesar A. Johnston
IPC分类号： G06F15/167
CPC分类号： H01M4/92 , H01M4/925 , H01M4/926 , H01M2008/1095
摘要： In managing and buffering packet data for transmission out of a host, descriptor ring data is pushed in from a host memory into a descriptor ring cache and cached therein. The descriptor ring data is processed to read a data packet descriptor, and a direct memory access is initiated to the host to read the data packet corresponding to the read data packet descriptor to a data transmission buffer. The data packet is written by the direct memory access into the data transmission buffer and cached therein. A return pointer is written to the host memory by the direct memory access indicating that the data packet descriptor has been read and the corresponding data packet has been transmitted. In managing and buffering packet data for transmission to a host, descriptor ring data is pushed in from a host memory into a descriptor ring cache and cached therein. Data packets for transmission to the host memory are received and cached in a data reception buffer. Data is read from the data reception buffer according to a data packet descriptor retrieved from the descriptor ring cache, and the data packet is written to a data reception queue within the host memory by a direct memory access. A return pointer is written to the host memory by the direct memory access indicating that the data packet has been written.
摘要翻译：在管理和缓存用于从主机发送的分组数据时，将描述符环数据从主机存储器推入描述符环形缓存并缓存在其中。处理描述符环数据以读取数据分组描述符，并且向主机发起直接存储器访问以将对应于读取数据分组描述符的数据分组读取到数据传输缓冲器。数据包通过直接存储器访问写入数据传输缓冲器并缓存在其中。通过直接存储器访问将返回指针写入主机存储器，指示已经读取数据分组描述符并且已经发送了相应的数据分组。在管理和缓冲分组数据以传输到主机时，将描述符环数据从主机存储器推入描述符环缓存并缓存在其中。用于发送到主机存储器的数据分组被接收并缓存在数据接收缓冲器中。从数据接收缓冲器根据从描述符环形高速缓存检索的数据包描述符读取数据，并通过直接存储器访问将数据包写入主机存储器内的数据接收队列。通过直接存储器访问将返回指针写入主机存储器，指示数据包已被写入。

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