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11. 发明授权

US5225697A dRAM cell and method 失效
标题翻译： dRAM单元格和方法
公开(公告)号：US5225697A
公开(公告)日：1993-07-06
申请号：US859286
申请日：1992-03-26
申请人： Satwinder S. Malhi , Gordon P. Pollack , William F. Richardson
发明人： Satwinder S. Malhi , Gordon P. Pollack , William F. Richardson
IPC分类号： H01L21/225 , H01L21/334 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L21/2257 , H01L27/10841 , H01L29/66181
摘要： A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.
摘要翻译：公开了一种dRAM单元和单元阵列及其制造方法，其中单元包括一个场效应晶体管和一个存储电容器，晶体管和电容器都形成在衬底中的沟槽中。晶体管源极，沟道和漏极以及一个电容器板基本垂直地形成在沟槽的主体衬底侧壁中，并且栅极和其它电容器板形成在插入到沟槽中的两个材料区域中，并且通过绝缘体与本体隔离层。信号电荷通过绝缘层通过体衬底源与电容器材料的电连接而被存储在插入到沟槽中的电容器材料上。在优选实施例中，衬底表面上的字线连接到形成栅极的插入区域的上部，并且衬底表面上的位线形成漏极。在位线和字线的交叉处形成沟槽和电池; 位线和字线形成垂直的平行线组。

12. 发明授权

US4939104A Method for forming a buried lateral contact 失效
标题翻译：形成埋入侧面接触的方法
公开(公告)号：US4939104A
公开(公告)日：1990-07-03
申请号：US122604
申请日：1987-11-17
申请人： Gordon P. Pollack , Donald M. Bordelon , William F. Richardson , Satwinder S. Malhi
发明人： Gordon P. Pollack , Donald M. Bordelon , William F. Richardson , Satwinder S. Malhi
IPC分类号： H01L21/225 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L21/2257 , H01L27/10841
摘要： The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells.One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate, which is provided by the described embodiment of the invention.Another embodiment of the present invention is an interconnection between a surface conductor and the surface of the substrate. This embodiment uses a conductive plug formed between the conductor and the substrate to form an interconnection using a minimum of surface area of the substrate.
摘要翻译：结合本发明的重要应用的dRAM单元的制造来描述本发明。所描述的单元提供单晶体管/单电容器dRAM单元结构和阵列，其中单元晶体管形成在包含单元电容器的基板沟槽的侧壁上; 字和位线跨过这个沟槽。晶体管在电容器顶部的堆叠产生在衬底上具有最小面积的电池，并解决了电池致密堆积的问题。一个电容器板和晶体管沟道和源极区域形成在沟槽的体侧壁中，并且晶体管栅极和电容器的另一个板都形成在沟槽中的多晶硅中，但是通过沟槽内的氧化物层彼此分离。信号电荷通过源区域与多晶硅电容器板的电连接而存储在多晶硅电容器板上，该多晶硅电容器板由本发明的所描述的实施例提供。本发明的另一实施例是表面导体与基片表面之间的互连。该实施例使用形成在导体和基板之间的导电插塞，以使用基板的最小表面积形成互连。

13. 发明授权

US4914739A Structure for contacting devices in three dimensional circuitry 失效
标题翻译：用于在三维电路中接触设备的结构
公开(公告)号：US4914739A
公开(公告)日：1990-04-03
申请号：US357658
申请日：1989-05-25
申请人： Satwinder S. Malhi
发明人： Satwinder S. Malhi
IPC分类号： H01L21/225 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L21/2257 , H01L27/10841
摘要： The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate. The described embodiment provides an electrical connection which facilitates the electrical characterization of the transistor and the capacitor by allowing separate connection to the transistor or the capacitor.
摘要翻译：结合本发明的重要应用的dRAM单元的制造来描述本发明。所描述的单元提供单晶体管/单电容器dRAM单元结构和阵列，其中单元晶体管形成在包含单元电容器的基板沟槽的侧壁上; 字和位线跨过这个沟槽。晶体管在电容器顶部的堆叠产生在衬底上具有最小面积的电池，并解决了电池致密堆积的问题。一个电容器板和晶体管沟道和源极区域形成在沟槽的体侧壁中，并且晶体管栅极和电容器的另一个板都形成在沟槽中的多晶硅中，但是通过沟槽内的氧化物层彼此分离。信号电荷通过源极区域与多晶硅电容器板的电连接而存储在多晶硅电容器板上。所描述的实施例提供了一种电连接，其通过允许与晶体管或电容器的单独连接来促进晶体管和电容器的电特性。

14. 发明授权

US4824793A Method of making DRAM cell with trench capacitor 失效
标题翻译：制造具有沟槽电容器的DRAM单元的方法
公开(公告)号：US4824793A
公开(公告)日：1989-04-25
申请号：US122559
申请日：1987-11-12
申请人： William F. Richardson , Satwinder S. Malhi
发明人： William F. Richardson , Satwinder S. Malhi
IPC分类号： H01L21/334 , H01L21/8242 , H01L21/265 , H01L21/302 , H01L27/10
CPC分类号： H01L27/10864 , H01L29/66181
摘要： A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel, and drain and one capacitor plate are formed essentially vertically in the sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench. Signal charge is stored on the material inserted into the trench. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface are formed as diffusions in the substrate which also form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.
摘要翻译：公开了一种dRAM单元和单元阵列及其制造方法，其中单元包括一个场效应晶体管和一个存储电容器，晶体管和电容器都形成在衬底中的沟槽中。晶体管源极，沟道和漏极以及一个电容器板基本上垂直地形成在沟槽的侧壁中，并且栅极和其它电容器板形成在插入到沟槽中的两个材料区域中。信号电荷存储在插入沟槽的材料上。在优选实施例中，衬底表面上的字线连接到形成栅极的插入区域的上部，衬底表面上的位线形成为也形成漏极的衬底中的扩散。在位线和字线的交叉处形成沟槽和电池; 位线和字线形成垂直的平行线组。

15. 发明授权

US4777147A Forming a split-level CMOS device 失效
标题翻译：形成分级CMOS设备
公开(公告)号：US4777147A
公开(公告)日：1988-10-11
申请号：US139536
申请日：1987-12-30
申请人： David B. Scott , Satwinder S. Malhi
发明人： David B. Scott , Satwinder S. Malhi
IPC分类号： H01L21/822 , H01L27/06 , H01L27/092 , H01L21/36
CPC分类号： H01L27/0922 , H01L21/8221 , H01L27/0688
摘要： A method for forming CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.
摘要翻译：一种用于形成CMOS器件的方法，其中NMOS器件是体器件，PMOS器件是SOI器件。 PMOS器件在绝缘体上硅层中形成它们的沟道区，优选在二氧化硅层上形成横向再结晶的退火多晶硅层。

16. 发明授权

US4651184A Dram cell and array 失效
标题翻译：戏剧单元格和阵列
公开(公告)号：US4651184A
公开(公告)日：1987-03-17
申请号：US646556
申请日：1984-08-31
申请人： Satwinder S. Malhi
发明人： Satwinder S. Malhi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/78 , H01L27/02 , H01L29/04 , H01L29/34
CPC分类号： H01L27/10841
摘要： A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one capacitor with both the transistor and the capacitor formed in a trench in a substrate. One capacitor plate and the transistor source are common and are formed in the lower portion of the trench sidewall. The transistor drain is formed in the upper portion of the trench sidewall to connect to a bit line on the substrate surface, and the channel is the vertical portion of the trench sidewall between the source and drain. A ground line runs past the transistor gate in the upper portion of the trench down into the lower portion of the trench to form the other capacitor plate.
摘要翻译：公开了一种dRAM单元和单元阵列，其中制造方法，其中该单元包括一个场效应晶体管和一个电容器，两个晶体管和电容器都形成在衬底中的沟槽中。一个电容器板和晶体管源是共同的，并且形成在沟槽侧壁的下部。晶体管漏极形成在沟槽侧壁的上部，以连接到衬底表面上的位线，并且沟道是源极和漏极之间的沟槽侧壁的垂直部分。接地线通过沟槽上部的晶体管栅极延伸到沟槽的下部，形成另一个电容器板。

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