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11. 发明申请

US20050152207A1 Semiconductor device using two types of power supplies supplying different potentials 有权
标题翻译：使用提供不同电位的两种电源的半导体器件
公开(公告)号：US20050152207A1
公开(公告)日：2005-07-14
申请号：US11075736
申请日：2005-03-10
申请人： Toshimi Ikeda , Kuninori Kawabata , Shuzo Otsuka
发明人： Toshimi Ikeda , Kuninori Kawabata , Shuzo Otsuka
IPC分类号： G11C8/08 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： A semiconductor device which is driven by a first potential, a second potential lower than the first potential, and a third potential lower than the second potential includes a first Pch transistor and a first Nch transistor connected in series between the first potential and the third potential, a second Pch transistor having a drain node thereof connected to a gate node of the first Nch transistor, and a second Nch transistor having a source node thereof connected to a source node of the second Pch transistor, wherein the drain node and gate node of the second Nch transistor are fixed to the second potential and the first potential, respectively.
摘要翻译：由第一电位，低于第一电位的第二电位和低于第二电位的第三电位驱动的半导体器件包括串联连接在第一电位和第三电位之间的第一Pch晶体管和第一N沟道晶体管，具有连接到第一N沟晶体管的栅极节点的漏极节点的第二Pch晶体管和其源极节点连接到第二Pch晶体管的源极节点的第二N沟道晶体管，其中漏极节点和栅极节点第二Nch晶体管分别被固定到第二电位和第一电位。

12. 发明授权

US06317353B1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06317353B1
公开(公告)日：2001-11-13
申请号：US09536449
申请日：2000-03-28
申请人： Toshimi Ikeda , Masato Matsumiya , Masato Takita
发明人： Toshimi Ikeda , Masato Matsumiya , Masato Takita
IPC分类号： G11C506
CPC分类号： G11C5/063 , G11C5/14
摘要： A power supply line is formed over a memory cell array which has arranged a plurality of memory cells using a metal wiring layer M1 which is disposed on the side closest to the memory cell array, of all the metal wiring layers. The power supply lines are formed over the memory cell array using not only an upper metal wiring layer M2 but the metal wiring layer M1 so that the wiring resistance of the power supply lines may decrease and a sufficient amount of current can be supplied to the power supply lines. Consequently, the circuits supplied with an electric current through the power supply lines become capable of high-speed operation. This is particularly effective for the high-speed operation of the circuits arranged around the memory cell array. The power supply line formed using the lower metal wiring layer M1 is connected over the memory cell array to a power supply line which is formed using the metal wiring layer M2 on the upper layer than the metal wiring layer M1. Therefore, the netlike configuration of the power supply lines can be made with higher density compared to conventional ones.
摘要翻译：电源线形成在存储单元阵列上，该存储单元阵列使用布置在最靠近存储单元阵列的一侧的金属布线层M1布置了多个存储单元。电源线不仅使用上金属布线层M2而且金属布线层M1形成在存储单元阵列的上方，使得电源线的布线电阻可能降低，并且能够向电源提供足够的电流量供应线。因此，通过电源线提供电流的电路变得能够高速运行。这对于布置在存储单元阵列周围的电路的高速操作特别有效。使用下金属布线层M1形成的电源线通过存储单元阵列连接到使用上层的金属布线层M2形成的电源线，而不是金属布线层M1。因此，与常规电源线相比，可以以更高的密度制造电源线的网状结构。

13. 发明授权

US06198686B1 Memory device having row decoder 有权
标题翻译：具有行解码器的存储器件
公开(公告)号：US06198686B1
公开(公告)日：2001-03-06
申请号：US09613583
申请日：2000-07-10
申请人： Masato Takita , Masato Matsumiya , Masatomo Hasegawa , Toshimi Ikeda
发明人： Masato Takita , Masato Matsumiya , Masatomo Hasegawa , Toshimi Ikeda
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C8/10 , G11C8/18 , G11C11/4076 , G11C11/4087
摘要： On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of-an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.
摘要翻译：一方面，通过缓冲器将行地址提供给行地址寄存器11，并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。另一方面，响应于发出激活命令，控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2，并且提供AS2以减少定时裕度，经由延迟电路20A到预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。每个锁存电路由具有设定输入和复位输入的NOR门组成，另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入，以接收对于所有者共同的多选择信号字解码器中的锁存电路。

14. 发明授权

US5994004A Levenson type phase shift photomask and manufacture method of semiconductor device using such photomask 失效
标题翻译：莱文森型相移光掩模和使用这种光掩模的半导体器件的制造方法
公开(公告)号：US5994004A
公开(公告)日：1999-11-30
申请号：US19743
申请日：1998-02-06
申请人： Yasuko Tabata , Satoru Asai , Toshimi Ikeda , Masato Matsumiya
发明人： Yasuko Tabata , Satoru Asai , Toshimi Ikeda , Masato Matsumiya
IPC分类号： G03F1/30 , G03F1/68 , H01L21/027 , G03F9/00
CPC分类号： G03F1/30
摘要： A photomask has a plurality of transparent regions defined in an opaque region and classified into first and second groups. Each of the transparent regions belonging to one of the first and second groups is provided with a phase shifter, so that the phase of light transmitted through the transparent region belonging to the first group becomes different from the phase of light transmitted through the transparent region belonging to the second group. The photomask includes: a pair of first transparent regions belonging to the first group and including linear portions disposed in parallel, a virtual straight line interconnecting one ends of the first transparent regions intersecting at a right angle with the extension direction of the linear portions; and a second transparent region belonging to the second group and disposed at the center between, and in parallel to, the linear portions of the pair of first transparent regions, the second transparent region including a linear thickportion and a linear thin portion, the linear thin portion being disposed in an area between the pair of first transparent regions and continuously coupled to the linear thick portion, and a connection portion between the thick and thin portions being indented from the virtual straight line toward the area between the pair of first transparent regions.
摘要翻译：光掩模具有限定在不透明区域中并被分类为第一和第二组的多个透明区域。属于第一组和第二组中的一个的透明区域中的每一个设置有移相器，使得透过属于第一组的透明区域的光的相位与透过透明区域的光的相位不同到第二组。光掩模包括：属于第一组的一对第一透明区域，并且包括平行设置的直线部分，将与直线部分的延伸方向成直角相交的第一透明区域的一端相互连接的虚拟直线; 以及属于第二组的第二透明区域，并且设置在一对第一透明区域的直线部分之间并且平行于中心，第二透明区域包括线性厚度部分和线状薄部分，线性薄片部分设置在一对第一透明区域之间的区域中并且连续地连接到线状厚部分，并且厚部分和薄部分之间的连接部分从假想直线向着该对第一透明区域之间的区域缩进。

15. 发明授权

US6111795A Memory device having row decoder 有权
标题翻译：具有行解码器的存储器件
公开(公告)号：US6111795A
公开(公告)日：2000-08-29
申请号：US342059
申请日：1999-06-29
申请人： Masato Takita , Masato Matsumiya , Masatomo Hasegawa , Toshimi Ikeda
发明人： Masato Takita , Masato Matsumiya , Masatomo Hasegawa , Toshimi Ikeda
IPC分类号： G11C11/407 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/4076 , G11C11/408 , G11C7/00
CPC分类号： G11C8/08 , G11C11/4076 , G11C11/4087 , G11C8/10 , G11C8/18
摘要： On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.
摘要翻译：一方面，通过缓冲器将行地址提供给行地址寄存器11，并且其输出经由互补信号生成电路15和预解码器16提供给字解码器17A。另一方面，响应于激活命令的发出，控制信号AS1经由延迟电路14提供给行地址寄存器11的时钟输入CK作为选通信号AS2，并且提供AS2以减少定时通过延迟电路20A将预解码器16的选通信号输入作为选通信号S2。 S2经由延迟电路20B提供给具有RS触发器2301至2332或锁存电路的字解码器17A的选通信号输入。每个锁存电路由具有设定输入和复位输入的NOR门组成，另一NOR门具有耦合以接收前NOR门的输出和另一组输入的输入，以接收对于所有者共同的多选择信号字解码器中的锁存电路。

16. 发明授权

US5661340A Dynamic random access memory having a stacked fin capacitor with reduced fin thickness 失效
标题翻译：动态随机存取存储器，其具有减小翅片厚度的堆叠鳍式电容器
公开(公告)号：US5661340A
公开(公告)日：1997-08-26
申请号：US141691
申请日：1993-10-26
申请人： Taiji Ema , Masaaki Higashitani , Toshimi Ikeda , Michiari Kawano , Hiroshi Nomura , Masaya Katayama , Masahiro Kuwamura
发明人： Taiji Ema , Masaaki Higashitani , Toshimi Ikeda , Michiari Kawano , Hiroshi Nomura , Masaya Katayama , Masahiro Kuwamura
IPC分类号： H01L21/8242 , H01L27/108 , H01L23/02 , H01L21/265
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for fabricating a dynamic random access memory comprises the steps of forming a diffusion region in a semiconductor substrate, providing an insulation layer on the semiconductor substrate, forming a contact hole in the insulation layer to expose the diffusion region at the contact hole, depositing a semiconductor layer on the insulation layer in the amorphous state such that the semiconductor layer establishes an intimate contact with the exposed diffusion region via the contact hole, patterning the semiconductor layer to form a capacitor electrode, depositing a dielectric film on the capacitor electrode such that said dielectric film covers the capacitor electrode; and depositing a semiconductor material to form an opposing electrode such that the opposing electrode buries the capacitor electrode underneath while establishing an intimate contact with the dielectric film that covers the capacitor electrode.
摘要翻译：一种用于制造动态随机存取存储器的方法，包括以下步骤：在半导体衬底中形成扩散区，在半导体衬底上提供绝缘层，在绝缘层上形成接触孔，露出接触孔处的扩散区，沉积在绝缘层上形成非晶状态的半导体层，使得半导体层经由接触孔与暴露的扩散区域形成紧密接触，构图半导体层以形成电容器电极，在电容器电极上沉积电介质膜，使得所述电介质膜覆盖电容器电极; 以及沉积半导体材料以形成相对的电极，使得相对电极将电容器电极埋在下面，同时与覆盖电容器电极的电介质膜形成紧密接触。

17. 发明授权

US5652167A Method of liquid treatment of micro-structures comprising structural members liable to be bent 失效
标题翻译：微结构液体处理方法，包括易于弯曲的结构构件
公开(公告)号：US5652167A
公开(公告)日：1997-07-29
申请号：US83371
申请日：1993-06-29
申请人： Motoo Nakano , Hiroshi Nomura , Masaya Katayama , Toshimi Ikeda , Fumihiko Inoue , Junichi Ishikawa , Masahiro Kuwamura
发明人： Motoo Nakano , Hiroshi Nomura , Masaya Katayama , Toshimi Ikeda , Fumihiko Inoue , Junichi Ishikawa , Masahiro Kuwamura
IPC分类号： B81B3/00 , H01L21/02 , H01L21/20 , H01L21/306 , H01L21/70
CPC分类号： B81B3/0005 , B81C1/0092 , H01L21/02063 , H01L28/87 , Y10T428/24744 , Y10T428/24942 , Y10T428/26 , Y10T428/8305
摘要： Micro-structures comprising at least a structural member, which is liable to be bent under an external force and formed so as to leave a space between the member and another member liable to be bent and/or other rigid component, are successfully treated using a treating liquid, without suffering permanent deformation resulting from the use of the treating liquid, by removing the micro-structures from the liquid to an environment having a pressure less than the atmospheric pressure; or displacing the micro-structures from the treating liquid to another treating liquid having a smaller surface tension than that of the former liquid, and then removing the micro-structures from the latter liquid; or drying the micro-structures removed from the treating liquid by exposing the same to vapor of a liquid having a smaller surface tension than that of the treating liquid; or removing the micro-structures from the treating liquid to the atmosphere, and drying them using an energy beam of high intensity or an ultrasonic wave. Micro-structures are also disclosed which comprise at least a member liable to be bent but are capable of avoiding permanent deformation of the member resulting from a treatment using a liquid.
摘要翻译：至少包括结构构件的微结构，其在外力下容易弯曲并且形成为在构件和易于弯曲的另一构件和/或其他刚性构件之间留下空间，成功地使用处理液体，而不会由于使用处理液而导致永久变形，通过将微结构从液体移除到具有小于大气压力的压力的环境中; 或将微结构从处理液体移位到具有比前者液体小的表面张力的另一处理液，然后从后一液体中除去微结构; 或者通过将从处理液中除去的微结构暴露于具有比处理液的表面张力小的液体的蒸汽，来干燥微结构; 或将微结构从处理液中除去至大气，并使用高强度能量束或超声波干燥它们。还公开了微结构，其包括至少一个易于弯曲的构件，但是能够避免由使用液体的处理引起的构件的永久变形。

18. 发明授权

US06650590B2 Semiconductor memory device with reduced its chip area and power consumption 有权
公开(公告)号：US06650590B2
公开(公告)日：2003-11-18
申请号：US10103141
申请日：2002-03-22
申请人： Tsuneo Inaba , Fumihiro Kohno , Kenji Tsuchida , Toshimi Ikeda
发明人： Tsuneo Inaba , Fumihiro Kohno , Kenji Tsuchida , Toshimi Ikeda
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C8/14
摘要： One (first level shift circuit) of first and second level shift circuits is provided in a local word-drive-line driving circuit located near memory cell arrays. The second level shift circuit is provided in a global word-drive-line driving circuit located remote from the memory cell arrays.

19. 发明授权

US5688712A Process for producing a semiconductor device 失效
标题翻译：半导体装置的制造方法
公开(公告)号：US5688712A
公开(公告)日：1997-11-18
申请号：US643938
申请日：1996-05-07
申请人： Taiji Ema , Toshimi Ikeda
发明人： Taiji Ema , Toshimi Ikeda
IPC分类号： H01L21/8244 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/11 , H01L21/70
CPC分类号： H01L27/105 , H01L27/10817 , H01L27/11 , H01L27/1116 , H01L28/86
摘要： A semiconductor device includes a semiconductor substrate having a memory cell area and a circuit area surrounding the memory cell area with a boundary area interposed therebetween. A first conductive layer covers the memory cell area and extends onto the boundary area. A first insulating layer covers the surrounding circuit area and part of the extended portion of the first conductive layer. A second insulating layer covering the first insulating layer and the first conductive layer. A throughhole is formed through the first and second insulating layers. A second conductive layer is electrically connected with another conductive layer via the throughhole and extends from the memory cell area to the surrounding circuit area. The process of producing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括具有存储单元区域的半导体衬底和围绕存储单元区域的电路区域，其间插入有边界区域。第一导电层覆盖存储单元区域并延伸到边界区域上。第一绝缘层覆盖周围电路区域和第一导电层的延伸部分的一部分。覆盖第一绝缘层和第一导电层的第二绝缘层。通过第一绝缘层和第二绝缘层形成通孔。第二导电层经由通孔与另一导电层电连接，并从存储单元区域延伸到周围电路区域。还公开了制造半导体器件的工艺。

20. 发明授权

US5591659A Process of producing a semiconductor device in which a height difference between a memory cell area and a peripheral area is eliminated 失效
标题翻译：制造其中消除了存储单元区域和外围区域之间的高度差的半导体器件的工艺
公开(公告)号：US5591659A
公开(公告)日：1997-01-07
申请号：US318261
申请日：1994-10-05
申请人： Taiji Ema , Toshimi Ikeda
发明人： Taiji Ema , Toshimi Ikeda
IPC分类号： H01L21/8242 , H01L21/8244 , H01L27/105 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10844 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L28/86
摘要： A semiconductor device comprising: a semiconductor substrate having a memory cell area containing a memory cell composed of a capacitor element, and a peripheral circuit area containing a peripheral circuit for controlling the memory cell; an insulating layer covering the peripheral circuit area and being absent in the memory cell area; protective layers effective in etching of the insulating layer and covering the top surfaces and side surfaces of word line conductor patters and bit line conductor patterns in the memory cell area; a contact hole having a circumference defined by one of the protective layers that covers side surfaces of the word line conductor patterns in the memory cell area, the contact hole extending to a diffused region in the semiconductor substrate; and a storage electrode of the capacitor element being connected to the diffused region through the contact hole. A process of producing the semiconductor device is also disclosed.
摘要翻译：一种半导体器件，包括：具有包含由电容器元件构成的存储单元的存储单元区域的半导体衬底和包含用于控制存储单元的外围电路的外围电路区域; 覆盖外围电路区域并且不存在于存储单元区域中的绝缘层; 保护层有效地蚀刻绝缘层并覆盖存储单元区域中的字线导体图案和位线导体图案的顶表面和侧表面; 接触孔，其具有由覆盖所述存储单元区域中的字线导体图案的侧表面的保护层之一限定的圆周，所述接触孔延伸到所述半导体衬底中的扩散区域; 并且电容器元件的存储电极通过接触孔连接到扩散区域。还公开了制造半导体器件的工艺。

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