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11. 发明申请

US20080016325A1 Using windowed register file to checkpoint register state 审中-公开
标题翻译：使用窗口寄存器文件进行检查点寄存器状态
公开(公告)号：US20080016325A1
公开(公告)日：2008-01-17
申请号：US11484970
申请日：2006-07-12
申请人： James P. Laudon , Adam R. Talcott , Sanjay Patel , Thirumalai S. Suresh
发明人： James P. Laudon , Adam R. Talcott , Sanjay Patel , Thirumalai S. Suresh
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3004 , G06F9/30087 , G06F9/3012 , G06F9/30127 , G06F9/30181 , G06F9/383 , G06F9/3857 , G06F9/3863
摘要： In one embodiment, a processor comprises a core configured to execute instructions; a register file comprising a plurality of storage locations; and a window management unit. The window management unit is configured to operate the plurality of storage locations as a plurality of windows, wherein register addresses encoded into the instructions identify storage locations among a subset of the plurality of storage locations that are within a current window. Additionally, the window management unit is configured to allocate a second window in response to a predetermined event. One of the current window and the second window serves as a checkpoint of register state, and the other one of the current window and the second window is updated in response to instructions processed subsequent to the checkpoint. The checkpoint may be restored if the speculative execution results are discarded.
摘要翻译：在一个实施例中，处理器包括被配置为执行指令的核心; 包括多个存储位置的寄存器文件; 和窗口管理单元。窗口管理单元被配置为将多个存储位置操作为多个窗口，其中编码到指令中的寄存器地址识别在当前窗口内的多个存储位置的子集之间的存储位置。另外，窗口管理单元被配置为响应于预定事件来分配第二窗口。当前窗口和第二窗口中的一个用作寄存器状态的检查点，并且响应于在检查点之后处理的指令来更新当前窗口和第二窗口中的另一个窗口。如果抛弃推测执行结果，则可以恢复检查点。

12. 发明授权

US06615343B1 Mechanism for delivering precise exceptions in an out-of-order processor with speculative execution 有权
标题翻译：在具有推测性执行的无序处理器中提供精确异常的机制
公开(公告)号：US06615343B1
公开(公告)日：2003-09-02
申请号：US09599227
申请日：2000-06-22
申请人： Adam R. Talcott , Daniel L. Liebholz , Sanjay Patel , Richard H. Larson
发明人： Adam R. Talcott , Daniel L. Liebholz , Sanjay Patel , Richard H. Larson
IPC分类号： G06F938
CPC分类号： G06F9/3861 , G06F9/3842
摘要： A method of handling an exception in a processor includes setting a state upon detection of an exception, signaling a trap for the exception if the state is set, and based on a class of the exception, processing the exception differently before signaling the trap. The method may include replaying an instruction causing the exception before signaling the trap for the exception based on the class of the exception. The method may include replaying the instruction causing the exception after the instruction causing the exception becomes an oldest, unretired instruction. The method may include signaling the trap for the exception after an instruction causing the exception becomes an oldest, unretired instruction. The method may include marking an instruction causing the exception as complete without issuing the instruction causing the exception. An apparatus for handling exceptions in a processor includes an instruction scheduler for setting a state upon detection of an exception and signaling a trap for the exception if the state is set. The instruction scheduler, based on a class of the exception, processes the exception differently before signaling the trap.
摘要翻译：在处理器中处理异常的方法包括在检测到异常时设置状态，如果状态被设置则发信号通知异常的陷阱，并且基于异常类，在发信号通知之前不同地处理异常。该方法可以包括在基于异常的类发送异常的陷阱之前重放导致异常的指令。该方法可以包括在导致异常的指令成为最旧的未命令指令之后重放导致异常的指令。该方法可以包括在导致异常的指令成为最旧的未命令指令之后发信号通知异常的陷阱。该方法可以包括将导致异常的指令标记为完整，而不发出导致异常的指令。用于在处理器中处理异常的装置包括指令调度器，用于在检测到异常时设置状态，并且如果状态被设置，则发送异常的陷阱。指令调度程序基于异常类，在通知陷阱之前处理异常。

13. 发明申请

US20080222383A1 Efficient On-Chip Accelerator Interfaces to Reduce Software Overhead 有权
标题翻译：高效的片上加速器接口，以减少软件开销
公开(公告)号：US20080222383A1
公开(公告)日：2008-09-11
申请号：US11684358
申请日：2007-03-09
申请人： Lawrence A. Spracklen , Santosh G. Abraham , Adam R. Talcott
发明人： Lawrence A. Spracklen , Santosh G. Abraham , Adam R. Talcott
IPC分类号： G06F9/34
CPC分类号： G06F12/1027 , G06F12/1036 , G06F2212/1024 , G06F2212/683
摘要： In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.
摘要翻译：在一个实施例中，处理器包括耦合到执行电路的执行电路和转换后备缓冲器（TLB）。执行电路被配置为执行具有数据操作数的存储指令; 并且所述执行电路被配置为生成作为执行所述存储指令的一部分的虚拟地址。所述TLB被耦合以接收所述虚拟地址并被配置为将所述虚拟地址转换为第一物理地址。此外，TLB被耦合以接收数据操作数并将数据操作数转换为第二物理地址。还可以在各种实施例中考虑硬件加速器，以及耦合到硬件加速器的处理器，方法和存储指令的计算机可读介质，其在执行时实现该方法的一部分。

14. 发明授权

US5935238A Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles 失效
标题翻译：通过当前和以前的指令束中的控制流指令从多个并发产生的提取地址中进行选择，包括预测和实际目标
公开(公告)号：US5935238A
公开(公告)日：1999-08-10
申请号：US878759
申请日：1997-06-19
申请人： Adam R. Talcott , Ramesh K. Panwar
发明人： Adam R. Talcott , Ramesh K. Panwar
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3861
摘要： A microprocessor is provided with an instruction fetch mechanism that simultaneously predicts multiple control-flow instructions. The instruction fetch unit farther is capable of handling multiple types of control-flow instructions. The instruction fetch unit uses predecode data and branch prediction data to select the next instruction fetch bundle address. If a branch misprediction is detected, a corrected branch target address is selected as the next fetch bundle address. If no branch misprediction occurs and the current fetch bundle includes a taken control-flow instruction, then the next fetch bundle address is selected based on the type of control-flow instruction detected. If the first taken control-flow instruction is a return instruction, a return address from the return address stack is selected as the next fetch bundle address. If the first taken control-flow instruction is an unconditional branch or predicted taken conditional branch, a predicted branch target address is selected as the next fetch bundle address. If no branch misprediction is detected and the current fetch bundle does not include a taking control-flow instruction, then a sequential address is selected as the next fetch bundle address.
摘要翻译：微处理器具有同时预测多个控制流指令的指令获取机制。指令提取单元能够处理多种类型的控制流程指令。指令提取单元使用预解码数据和分支预测数据来选择下一个指令获取束地址。如果检测到分支错误预测，则选择校正的分支目标地址作为下一个获取束地址。如果没有发生分支错误预测，并且当前的提取束包括所采取的控制流指令，则基于检测到的控制流指令的类型来选择下一个提取束地址。如果第一个采取的控制流程指令是一个返回指令，则返回地址堆栈的返回地址将被选择作为下一个提取包地址。如果第一个采取的控制流程指令是无条件分支或预测的条件分支，则选择预测的分支目标地址作为下一个获取束地址。如果没有检测到分支错误预测，并且当前的提取包不包括获取控制流程指令，则选择顺序地址作为下一个提取包地址。

15. 发明授权

US06948055B1 Accuracy of multiple branch prediction schemes 有权
标题翻译：多分支预测方案的准确性
公开(公告)号：US06948055B1
公开(公告)日：2005-09-20
申请号：US09685270
申请日：2000-10-09
申请人： Adam R. Talcott
发明人： Adam R. Talcott
IPC分类号： G06F9/38
CPC分类号： G06F9/3844
摘要： A method and apparatus of improving prediction accuracy of a branch instruction scheme includes reading an individual instruction in a current set of instructions, fetching the individual instruction when an instruction fetch unit determines that the individual instruction is valid, and allowing the instruction fetch unit to use an index address for the fetched individual instruction. A method and apparatus of improving branch prediction accuracy includes receiving a set of instructions having an assigned address, making a prediction for a branch instruction in the set of instructions using the assigned address, and retaining the assigned address for the branch instruction in the set of instructions.
摘要翻译：一种改善分支指令方案的预测精度的方法和装置，包括：当指令提取单元确定单独指令有效时，读取当前指令集中的单独指令，取出单独指令，并允许指令提取单元使用提取的单独指令的索引地址。一种提高分支预测精度的方法和装置包括：接收具有分配地址的一组指令，使用分配的地址对该组指令中的分支指令进行预测，并将分配指令的分配地址保留在说明。

16. 发明授权

US06272623B1 Methods and apparatus for branch prediction using hybrid history with index sharing 有权
标题翻译：使用索引共享的混合历史进行分支预测的方法和装置
公开(公告)号：US06272623B1
公开(公告)日：2001-08-07
申请号：US09236081
申请日：1999-01-25
申请人： Adam R. Talcott
发明人： Adam R. Talcott
IPC分类号： G06F938
CPC分类号： G06F9/3806 , G06F9/3848
摘要： A branch prediction scheme predicts whether a computer instruction will cause a branch to a non-sequential instruction. A prediction counter is selected by performing an exclusive or (XOR) operation between bits from an instruction address and a hybrid history. The hybrid history, in turn, is derived by concatenating bits from a global history register with bits from a local branch history table. The bits from the local branch history table are accessed by using bits from the instruction address.
摘要翻译：分支预测方案预测计算机指令是否将导致分支到非顺序指令。通过在指令地址和混合历史的位之间执行异或（XOR）操作来选择预测计数器。混合历史又是通过将来自全局历史寄存器的比特与来自本地分支历史表的比特连接而得到的。通过使用指令地址中的位来访问本地分支历史表中的位。

17. 发明授权

US5964869A Instruction fetch mechanism with simultaneous prediction of control-flow instructions 失效
标题翻译：指令获取机制，同时预测控制流指令
公开(公告)号：US5964869A
公开(公告)日：1999-10-12
申请号：US878753
申请日：1997-06-19
申请人： Adam R. Talcott , Ramesh K. Panwar
发明人： Adam R. Talcott , Ramesh K. Panwar
IPC分类号： G06F9/38
CPC分类号： G06F9/382 , G06F9/30054 , G06F9/3806 , G06F9/3844 , G06F9/3861
摘要： A microprocessor is provided with an instruction fetch mechanism that simultaneously predicts multiple control-flow instructions. The instruction fetch unit further is capable of handling multiple types of control-flow instructions. The instruction fetch unit uses predecode data and branch prediction data to select the next instruction fetch bundle address. If a branch misprediction is detected, a corrected branch target address is selected as the next fetch bundle address. If no branch misprediction occurs and the current fetch bundle includes a taken control-flow instruction, then the next fetch bundle address is selected based on the type of control-flow instruction detected. If the first taken control-flow instruction is a return instruction, a return address from the return address stack is selected as the next fetch bundle address. If the first taken control-flow instruction is an unconditional branch or predicted taken conditional branch, a predicted branch target address is selected as the next fetch bundle address. If no branch misprediction is detected and the current fetch bundle does not include a taking control-flow instruction, then a sequential address is selected as the next fetch bundle address.
摘要翻译：微处理器具有同时预测多个控制流指令的指令获取机制。指令获取单元还能够处理多种类型的控制流程指令。指令提取单元使用预解码数据和分支预测数据来选择下一个指令获取束地址。如果检测到分支错误预测，则选择校正的分支目标地址作为下一个获取束地址。如果没有发生分支错误预测，并且当前的提取束包括所采取的控制流指令，则基于检测到的控制流指令的类型来选择下一个提取束地址。如果第一个采取的控制流程指令是一个返回指令，则返回地址堆栈的返回地址将被选择作为下一个提取包地址。如果第一个采取的控制流程指令是无条件分支或预测的条件分支，则选择预测的分支目标地址作为下一个获取束地址。如果没有检测到分支错误预测，并且当前的提取包不包括获取控制流程指令，则选择顺序地址作为下一个提取包地址。

18. 发明授权

US08826241B2 Instruction sampling in a multi-threaded processor 有权
标题翻译：多线程处理器中的指令采样
公开(公告)号：US08826241B2
公开(公告)日：2014-09-02
申请号：US10780264
申请日：2004-02-16
申请人： Mario I. Wolczko , Adam R. Talcott
发明人： Mario I. Wolczko , Adam R. Talcott
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F9/3851
摘要： A method of sampling instructions executing in a multi-threaded processor which includes selecting an instruction for sampling, storing information relating to the instruction, determining whether the instruction includes an event of interest, and reporting the instruction if the instruction includes an event of interest on a per-thread basis. The event of interest includes information relating to a thread to which the instruction is bound.
摘要翻译：一种在多线程处理器中执行的采样指令的方法，包括选择采样指令，存储与指令有关的信息，确定指令是否包括感兴趣的事件，以及如果指令包括感兴趣的事件，则报告指令每个线程的基础。感兴趣的事件包括与指令绑定的线程有关的信息。

19. 发明授权

US07827383B2 Efficient on-chip accelerator interfaces to reduce software overhead 有权
标题翻译：高效的片上加速器接口，以减少软件开销
公开(公告)号：US07827383B2
公开(公告)日：2010-11-02
申请号：US11684358
申请日：2007-03-09
申请人： Lawrence A. Spracklen , Santosh G. Abraham , Adam R. Talcott
发明人： Lawrence A. Spracklen , Santosh G. Abraham , Adam R. Talcott
IPC分类号： G06F9/34 , G06F12/08
CPC分类号： G06F12/1027 , G06F12/1036 , G06F2212/1024 , G06F2212/683
摘要： In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.
摘要翻译：在一个实施例中，处理器包括耦合到执行电路的执行电路和转换后备缓冲器（TLB）。执行电路被配置为执行具有数据操作数的存储指令; 并且所述执行电路被配置为生成作为执行所述存储指令的一部分的虚拟地址。所述TLB被耦合以接收所述虚拟地址并被配置为将所述虚拟地址转换为第一物理地址。此外，TLB被耦合以接收数据操作数并将数据操作数转换为第二物理地址。还可以在各种实施例中考虑硬件加速器，以及耦合到硬件加速器的处理器，方法和存储指令的计算机可读介质，其在被执行时实现该方法的一部分。

20. 发明授权

US06934830B2 Method and apparatus for reducing register file access times in pipelined processors 有权
标题翻译：用于在流水线处理器中减少寄存器文件访问时间的方法和装置
公开(公告)号：US06934830B2
公开(公告)日：2005-08-23
申请号：US10259721
申请日：2002-09-26
申请人： Sudarshan Kadambi , Adam R. Talcott , Wayne I. Yamamoto
发明人： Sudarshan Kadambi , Adam R. Talcott , Wayne I. Yamamoto
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30138 , G06F9/3824 , G06F9/3857
摘要： One embodiment of the present invention provides a system that reduces the time required to access registers from a register file within a processor. During operation, the system receives an instruction to be executed, wherein the instruction identifies at least one operand to be accessed from the register file. Next, the system looks up the operands in a register pane, wherein the register pane is smaller and faster than the register file and contains copies of a subset of registers from the register file. If the lookup is successful, the system retrieves the operands from the register pane to execute the instruction. Otherwise, if the lookup is not successful, the system retrieves the operands from the register file, and stores the operands into the register pane. This triggers the system to reissue the instruction to be executed again, so that the re-issued instruction retrieves the operands from the register pane.
摘要翻译：本发明的一个实施例提供一种减少从处理器内的寄存器文件访问寄存器所需的时间的系统。在操作期间，系统接收要执行的指令，其中该指令从该寄存器文件中识别要访问的至少一个操作数。接下来，系统在寄存器窗格中查找操作数，其中寄存器窗格比寄存器文件更小和更快，并且包含寄存器文件中寄存器子集的副本。如果查找成功，系统将从寄存器窗格中检索操作数，执行指令。否则，如果查找不成功，系统将从寄存器文件中检索操作数，并将操作数存储到寄存器窗格中。这将触发系统重新发出要再次执行的指令，以便重新发出的指令从寄存器窗格中检索操作数。

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