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11. 发明授权

US07392270B2 Apparatus and method for reducing the latency of sum-addressed shifters 有权
标题翻译：用于减少和寻址移位器的延迟的装置和方法
公开(公告)号：US07392270B2
公开(公告)日：2008-06-24
申请号：US10902475
申请日：2004-07-29
申请人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Christian Jacobi , Silvia Melitta Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F7/00 , G06F7/38
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译：本发明提供了作为多个数字的函数的移位量的计算。至少一个解码器和至少一个加法器并联耦合。移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。

12. 发明申请

US20090024684A1 Method for Controlling Rounding Modes in Single Instruction Multiple Data (SIMD) Floating-Point Units 有权
标题翻译：用于控制单指令多数据（SIMD）浮点单元中舍入模式的方法
公开(公告)号：US20090024684A1
公开(公告)日：2009-01-22
申请号：US12238500
申请日：2008-09-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/483
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

13. 发明申请

US20070038693A1 Method and Processor for Performing a Floating-Point Instruction Within a Processor 审中-公开
标题翻译：在处理器内执行浮点指令的方法和处理器
公开(公告)号：US20070038693A1
公开(公告)日：2007-02-15
申请号：US11462069
申请日：2006-08-03
申请人： Christian Jacobi , Matthias Klein , Silvia Mueller , Matthias Pflanz , Jochen Preiss
发明人： Christian Jacobi , Matthias Klein , Silvia Mueller , Matthias Pflanz , Jochen Preiss
IPC分类号： G06F7/38
CPC分类号： G06F7/49936
摘要： The invention relates to a method for performing floating-point instructions within a processor of a data processing system is described, wherein an input of said floating-point instruction comprises a normal or a denormal floating-point number. Said method comprises the steps of storing said floating-point number, normalization of said floating-point number by counting the leading zeros of the mantissa, shifting the fraction part to the left by the number of leading zeros and simultaneously decrementing the exponent by one for every position that the fraction part is shifted to the left, wherein it the input is a normal floating point number the normalization is done after counting no leading zero of the mantissa, execution of a floating point instruction, wherein said normalized floating-point number is utilized as input for the floating point instruction, and storing of a floating-point result. Furthermore a processor to be used to perform said method is described.
摘要翻译：本发明涉及一种用于在数据处理系统的处理器内执行浮点指令的方法，其中所述浮点指令的输入包括正常或非正常浮点数。所述方法包括以下步骤：存储所述浮点数，通过对尾数的前导零进行计数来归一化所述浮点数，将分数部分向左移动前导零的数量，同时将指数递减1，分数部分向左移动的每个位置，其中输入是普通浮点数，在不计算尾数的前导零之后进行归一化，执行浮点指令，其中所述标准化浮点数为用作浮点指令的输入，以及浮点结果的存储。此外，描述了用于执行所述方法的处理器。

14. 发明申请

US20060184601A1 Floating point unit with fused multiply add and method for calculating a result with a floating point unit 失效
标题翻译：具有融合乘法的浮点单元和用浮点单元计算结果的方法
公开(公告)号：US20060184601A1
公开(公告)日：2006-08-17
申请号：US11055812
申请日：2005-02-11
申请人： Son Trong , Juergen Haess , Christian Jacobi , Klaus Kroener , Silvia Mueller , Jochen Preiss
发明人： Son Trong , Juergen Haess , Christian Jacobi , Klaus Kroener , Silvia Mueller , Jochen Preiss
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F7/5443
摘要： The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of the alignment logic (3) output have all the same value in order to: a) control the carry logic of the adder logic (5) and/or b) control a stage of the normalization logic (6).
摘要翻译：本发明提出了一种具有融合乘法运算的浮点单元（1），具有一个加数运算数（eb，fb）和两个被乘数运算符（ea，fa; ec，fc），其中移位量逻辑（2）基于操作数（ea，eb和ec）的指数利用对准逻辑（3）计算对准偏移量，该对准逻辑（3）使用对准移位量来对齐加数操作数的分数（fb）与乘法逻辑（4）将乘法器操作数（fa，fc）的分数与加法器逻辑（5）相乘，该逻辑（5）将对准逻辑（3）和乘法逻辑（4）的输出与归一化逻辑（6）进行归一化，归一化逻辑（6）加法器逻辑（5）的特征在于提供一个前导零逻辑（7），其计算加法运算数（fb）的分数的前导零的数量，并且提供比较逻辑（8）其基于前导零的数量和对准移位量计算选择信号i 指出对齐逻辑（3）输出的最高有效位是否具有全部相同的值，以便：a）控制加法器逻辑（5）的进位逻辑和/或b）控制归一化逻辑（6 ）。

15. 发明申请

US20070050435A1 Leading-Zero Counter and Method to Count Leading Zeros 审中-公开
标题翻译：领先的零计数器和计算领先零的方法
公开(公告)号：US20070050435A1
公开(公告)日：2007-03-01
申请号：US11459663
申请日：2006-07-25
申请人： Christian Jacobi , Silvia Mueller , Jochen Preiss , Kai Weber
发明人： Christian Jacobi , Silvia Mueller , Jochen Preiss , Kai Weber
IPC分类号： G06F15/00
CPC分类号： G06F7/74
摘要： The present invention relates to a circuit comprising a Leading Zero Counter (LZC) sub-circuit driving a second sub-circuit, like a shifter or arbiter. Shifter circuits or arbiter circuits operating with fewer stages than before have a smaller delay since every stage can select between more than two inputs. This reduces the overall delay of the shifter, arbiter, etc. But for state-of-the art binary LZC circuits this requires a complex recoding between LZC and shifter circuit. In order to provide an improved leading zero circuit having an output which allows a simpler control of a post-connected sub-circuit having two or more stages and having at least one stage with three or more inputs, it is proposed to provide a LZC circuitry providing an output consisting of two or more unary encoded substrings. This removes the requirement for a recoder between LZC and shifter.
摘要翻译：本发明涉及一种包括驱动第二子电路的前导零计数器（LZC）子电路的电路，如移相器或仲裁器。移动器电路或仲裁器电路的运行次数比以前更少，延迟较小，因为每个阶段都可以在两个以上的输入之间进行选择。这减少了移位器，仲裁器等的总体延迟。但是对于最先进的二进制LZC电路，这需要LZC和移位器电路之间的复杂重新编码。为了提供具有输出的改进的前导零电路，其允许更简单地控制具有两个或更多个级的后连接子电路并且具有至少一个具有三个或更多个输入的级，所以建议提供一种LZC电路提供由两个或更多个一元编码的子串组成的输出。这消除了对LZC和移位器之间的重新编码器的要求。

16. 发明授权

US10437602B2 Program interruption filtering in transactional execution 有权
公开(公告)号：US10437602B2
公开(公告)日：2019-10-08
申请号：US13524839
申请日：2012-06-15
申请人： Dan F. Greiner , Christian Jacobi , Marcel Mitran , Timothy J. Slegel
发明人： Dan F. Greiner , Christian Jacobi , Marcel Mitran , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48
摘要： Program exception conditions cause a transaction to abort and typically result in an interruption in which the operating system obtains control. A program interruption filtering control is provided to selectively present the interrupt. That is, the interrupt from the program exception condition may or may not be presented depending at least on the program interruption filtering control and a transaction class associated with the program exception condition. The program interruption filtering control is provided by a TRANSACTION BEGIN instruction.

17. 发明授权

US09740549B2 Facilitating transaction completion subsequent to repeated aborts of the transaction 有权
公开(公告)号：US09740549B2
公开(公告)日：2017-08-22
申请号：US13524857
申请日：2012-06-15
申请人： Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Timothy J. Slegel
发明人： Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Timothy J. Slegel
IPC分类号： G06F7/00 , G06F17/00 , G06F11/07 , G06F17/30 , G06F9/46 , G06F13/24
CPC分类号： G06F11/076 , G06F9/466 , G06F11/0721 , G06F13/24 , G06F17/30371
摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

18. 发明授权

US09710266B2 Instruction to compute the distance to a specified memory boundary 有权
公开(公告)号：US09710266B2
公开(公告)日：2017-07-18
申请号：US13421451
申请日：2012-03-15
申请人： Jonathan D. Bradbury , Michael K. Gschwind , Christian Jacobi , Eric M. Schwarz , Timothy J. Slegel
发明人： Jonathan D. Bradbury , Michael K. Gschwind , Christian Jacobi , Eric M. Schwarz , Timothy J. Slegel
IPC分类号： G06F9/38 , G06F9/30 , G06F9/355
CPC分类号： G06F9/30043 , G06F9/3001 , G06F9/3004 , G06F9/30076 , G06F9/355 , G06F9/3824 , G06F9/3861
摘要： A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined.

19. 发明授权

US09459867B2 Instruction to load data up to a specified memory boundary indicated by the instruction 有权
标题翻译：将数据加载到指令指定的指定内存边界的指令
公开(公告)号：US09459867B2
公开(公告)日：2016-10-04
申请号：US13421456
申请日：2012-03-15
申请人： Jonathan D. Bradbury , Michael K. Gschwind , Christian Jacobi , Eric M. Schwarz , Timothy J. Slegel
发明人： Jonathan D. Bradbury , Michael K. Gschwind , Christian Jacobi , Eric M. Schwarz , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F9/38 , G06F9/455
CPC分类号： G06F9/30043 , G06F9/30007 , G06F9/30036 , G06F9/3004 , G06F9/30047 , G06F9/30098 , G06F9/3013 , G06F9/30145 , G06F9/3824 , G06F9/3861 , G06F9/45516
摘要： A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary.
摘要翻译：加载到块提供了将可变数量的字节数据加载到寄存器中，同时确保指定的存储器边界未被越过。边界可以指定多种方式，包括但不限于指令文本中的可变值，编码在操作码中的固定指令文本值或基于寄存器的边界。

20. 发明授权

US09336046B2 Transaction abort processing 有权
标题翻译：事务中止处理
公开(公告)号：US09336046B2
公开(公告)日：2016-05-10
申请号：US13524877
申请日：2012-06-15
申请人： Dan F. Greiner , Christian Jacobi , Timothy J. Slegel
发明人： Dan F. Greiner , Christian Jacobi , Timothy J. Slegel
IPC分类号： G06F9/46 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30098 , G06F9/3004 , G06F9/30087 , G06F9/30145 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3861 , G06F9/466
摘要： A transaction executing within a computing environment ends prior to completion; i.e., execution is aborted. Pursuant to aborting execution, a hardware transactional execution CPU mode is exited, and one or more of the following is performed: restoring selected registers; committing nontransactional stores on abort; branching to a transaction abort program status word specified location; setting a condition code and/or abort code; and/or preserving diagnostic information.
摘要翻译：在计算环境中执行的事务在完成之前结束; 即执行中止。根据中止执行，退出硬件事务执行CPU模式，执行以下一个或多个操作：恢复所选择的寄存器; 在中止时承诺非事务性商店; 分支到事务中止程序状态字指定位置; 设置条件代码和/或中止代码; 和/或保存诊断信息。

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