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11. 发明授权

US06773508B2 Single crystal silicon carbide thin film fabrication method and fabrication apparatus of the same 失效
标题翻译：单晶碳化硅薄膜制造方法及其制造装置
公开(公告)号：US06773508B2
公开(公告)日：2004-08-10
申请号：US10159111
申请日：2002-06-03
申请人： Katsutoshi Izumi , Motoi Nakao , Yoshiaki Ohbayashi , Keiji Mine , Fumihiko Jobe
发明人： Katsutoshi Izumi , Motoi Nakao , Yoshiaki Ohbayashi , Keiji Mine , Fumihiko Jobe
IPC分类号： C30B2504
CPC分类号： C30B25/02 , C30B29/36
摘要： To economically and easily fabricate a single crystal silicon carbide thin film. The apparatus for fabricating a single crystal silicon carbide thin film comprises a film-formation chamber 200 adapted to receive a SOI substrate 100 for film-formation, a gas supply means 300 for supplying various gases G1 to G4 necessary to fabricate a single crystal silicon carbide thin film to the film-formation chamber 200, a gas treatment means 500 for treating argon gas as an inert gas G1, propane gas as a hydrocarbon-based gas G2, hydrogen gas as a carrier gas, and oxygen gas G4 supplied to the film-formation chamber 200, and a temperature control means 400 for controlling the temperature of the film-formation chamber 200.
摘要翻译：经济地制造单晶碳化硅薄膜。用于制造单晶碳化硅薄膜的装置包括适于接收用于成膜的SOI衬底100的成膜室200，用于供应制造单晶碳化硅所需的各种气体G1至G4的气体供给装置300 薄膜形成室200，用于处理氩气作为惰性气体G1的气体处理装置500，作为烃类气体G2的丙烷气体，作为载气的氢气和供给到膜的氧气G4 以及用于控制成膜室200的温度的温度控制装置400。

12. 发明申请

US20100252837A1 METHOD FOR PRODUCING SINGLE CRYSTAL SiC SUBSTRATE AND SINGLE CRYSTAL SiC SUBSTRATE PRODUCED BY THE SAME 有权
标题翻译：用于生产单晶SiC衬底和由其生产的单晶SiC衬底的方法
公开(公告)号：US20100252837A1
公开(公告)日：2010-10-07
申请号：US12742413
申请日：2008-10-29
申请人： Katsutoshi Izumi , Takashi Yokoyama
发明人： Katsutoshi Izumi , Takashi Yokoyama
IPC分类号： H01L29/24 , H01L21/22 , H01L21/04
CPC分类号： H01L21/265 , C30B1/10 , C30B29/36 , H01L21/02381 , H01L21/02488 , H01L21/02529 , H01L21/02614 , H01L21/76251
摘要： A single crystal SiC substrate is produced with low cost in which a polycrystalline SiC substrate with relatively low cost is used as a base material substrate where the single crystal SiC substrate has less strain, good crystallinity and large size. The method including a P-type ion introduction step for implanting P-type ions from a side of a surface Si layer 3 into an SOI substrate 1 in which the surface Si layer 3 and an embedded oxide layer 4 having a predetermined thickness are foamed on an Si base material layer 2 to convert the embedded oxide layer 4 into a PSG layer 6 to lower a softening point, and an SiC forming step for heating the SOI substrate 1 having the PSG layer 6 formed therein in an atmosphere of hydrocarbon-based gas to convert the surface Si layer 3 into SiC, and thereafter, cooling the resulting substrate to foam a single crystal SiC layer 5 on a surface thereof.
摘要翻译：以低成本制造单晶SiC衬底，其中使用具有较低成本的多晶SiC衬底作为单晶SiC衬底具有较小的应变，良好的结晶度和较大尺寸的基底衬底。包括用于将P型离子从表面Si层3的一侧注入到其中表面Si层3和具有预定厚度的嵌入氧化物层4发泡的SOI衬底1的P型离子引入步骤的方法将嵌入的氧化物层4转化为PSG层6以降低软化点的Si基材层2，以及在烃类气体的气氛中加热形成有PSG层6的SOI衬底1的SiC形成工序将表面Si层3转化成SiC，然后冷却所得到的基板，使单晶SiC层5在其表面上发泡。

13. 发明授权

US07393763B2 Manufacturing method of monocrystalline gallium nitride localized substrate 失效
标题翻译：单晶氮化镓局部衬底的制造方法
公开(公告)号：US07393763B2
公开(公告)日：2008-07-01
申请号：US11055985
申请日：2005-02-14
申请人： Katsutoshi Izumi , Motoi Nakao , Yoshiaki Ohbayashi , Keiji Mine , Seisaku Hirai , Fumihiko Jobe , Tomoyuki Tanaka
发明人： Katsutoshi Izumi , Motoi Nakao , Yoshiaki Ohbayashi , Keiji Mine , Seisaku Hirai , Fumihiko Jobe , Tomoyuki Tanaka
IPC分类号： H01L21/36
CPC分类号： C30B25/02 , C30B29/406 , H01L21/02381 , H01L21/02447 , H01L21/0254 , H01L21/02639
摘要： There is provided a monocrystalline gallium nitride localized substrate suitable for manufacturing electronic-optical united devices in which electronic devices and optical devices are mixedly mounted on the same silicon substrate.An area in which monocrystalline gallium nitride 410 is grown is locally present on a silicon substrate 100 by forming silicon carbide 200 on the silicon substrate 100 to locally form the monocrystalline gallium nitride 410 on the above-mentioned silicon carbide 200. Silicon nitride 220 is used as a mask in forming the above-mentioned monocrystalline gallium nitride 410.
摘要翻译：提供了适用于制造电子器件和光学器件混合安装在同一硅衬底上的电子 - 光学联合器件的单晶氮化镓局部衬底。单晶氮化镓410生长的区域通过在硅衬底100上形成碳化硅200而在硅衬底100上局部存在，以在上述碳化硅200上局部形成单晶氮化镓410。在形成上述单晶氮化镓410时，使用氮化硅220作为掩模。

14. 发明授权

US07128788B2 Manufacturing apparatus for buried insulating layer-type semiconductor silicon carbide substrate 有权
标题翻译：埋层绝缘层型半导体碳化硅基板的制造装置
公开(公告)号：US07128788B2
公开(公告)日：2006-10-31
申请号：US10802806
申请日：2004-03-18
申请人： Katsutoshi Izumi , Motoi Nakao , Yoshiaki Ohbayashi , Keiji Mine , Seisaku Hirai , Fumihiko Jobe , Tomoyuki Tanaka
发明人： Katsutoshi Izumi , Motoi Nakao , Yoshiaki Ohbayashi , Keiji Mine , Seisaku Hirai , Fumihiko Jobe , Tomoyuki Tanaka
IPC分类号： C23C16/00 , H01L21/20 , H01L21/36
CPC分类号： H01L21/7624 , H01L21/02378 , H01L21/02381 , H01L21/02488 , H01L21/02529 , H01L21/02532 , H01L21/02639 , H01L21/02656 , H01L21/0445 , H01L21/7602 , H01L21/76251
摘要： A manufacturing method for a buried insulating layer-type semiconductor silicon carbide substrate comprises the step of placing an SOI substrate 100, which has a surface silicon layer 130 of a predetermined thickness and a buried insulator 120, in a heating furnace 200 and of increasing the temperature of the atmosphere within heating furnace 200 while supplying a mixed gas (G1+G2) of a hydrogen gas G1 and of a hydrocarbon gas G2 into heating furnace 200, thereby, of metamorphosing surface silicon layer 130 of SOI substrate 100 into a single crystal silicon carbide thin film 140.
摘要翻译：掩埋绝缘层型半导体碳化硅衬底的制造方法包括将具有预定厚度的表面硅层130和掩埋绝缘体120的SOI衬底100放置在加热炉200中的步骤，同时向加热炉200供给氢气G 1和烃气G 2的混合气体（G 1 + G 2），从而将SOI衬底100的变形表面硅层130 成为单晶碳化硅薄膜140。

15. 发明申请

US20050136611A1 Manufacturing device for buried insulating layer type single crystal silicon carbide substrate 失效
标题翻译：埋层绝缘层型单晶碳化硅基板制造装置
公开(公告)号：US20050136611A1
公开(公告)日：2005-06-23
申请号：US11050683
申请日：2005-02-07
申请人： Katsutoshi Izumi , Motoi Nakao , Yoshiaki Ohbayashi , Keiji Mine , Seisaku Hirai , Fumihiko Jobe , Tomoyuki Tanaka
发明人： Katsutoshi Izumi , Motoi Nakao , Yoshiaki Ohbayashi , Keiji Mine , Seisaku Hirai , Fumihiko Jobe , Tomoyuki Tanaka
IPC分类号： C30B29/36 , H01L21/02 , H01L21/04 , H01L21/20 , H01L21/205 , H01L21/76 , H01L21/762 , H01L27/12 , H01L21/30
CPC分类号： H01L21/7624 , C23C16/0218 , C23C16/0236 , C23C16/325 , C23C16/482 , C30B1/10 , C30B29/36 , H01L21/02381 , H01L21/02491 , H01L21/02529 , H01L21/02614 , H01L21/0445 , H01L21/2007 , H01L21/7602 , Y10T29/41
摘要： Provided is a manufacturing method of a buried insulating layer type semiconductor silicon carbide substrate excellent in flatness of an interfaces in contact the insulating layer and a manufacturing device thereof. In the manufacturing device, an SOI substrate having a buried insulating layer positioned on a silicon substrate and a surface silicon layer formed on this buried insulating layer is placed in this film formation chamber. The manufacturing device includes: the film formation chamber in which the SOI substrate is placed; a gas supplying unit for supplying various types of gasses required for the manufacturing of a buried insulating layer type semiconductor silicon carbide substrate into the film formation chamber; an infrared ray irradiating unit for irradiating the surface silicon layer of the SOI substrate with infrared rays; and a control part for controlling the gas supplying unit and the infrared ray irradiating unit.
摘要翻译：提供一种绝缘层与其制造装置接触的界面的平坦度优异的掩埋绝缘层型半导体碳化硅基板的制造方法。在制造装置中，在该成膜室中配置具有位于硅衬底上的埋入绝缘层和形成在该埋置绝缘层上的表面硅层的SOI衬底。制造装置包括：成膜室，其中放置SOI基板; 气体供给单元，用于将掩模绝缘层型半导体碳化硅基板的制造所需的各种气体供给到成膜室中; 红外线照射单元，其用红外线照射SOI衬底的表面硅层; 以及用于控制气体供给单元和红外线照射单元的控制部。

16. 发明授权

US08603901B2 Method for producing single crystal SiC substrate and single crystal SiC substrate produced by the same 有权
标题翻译：制造单晶SiC衬底和单晶SiC衬底的方法
公开(公告)号：US08603901B2
公开(公告)日：2013-12-10
申请号：US12742413
申请日：2008-10-29
申请人： Katsutoshi Izumi , Takashi Yokoyama
发明人： Katsutoshi Izumi , Takashi Yokoyama
IPC分类号： H01L29/24 , H01L21/22 , H01L21/04
CPC分类号： H01L21/265 , C30B1/10 , C30B29/36 , H01L21/02381 , H01L21/02488 , H01L21/02529 , H01L21/02614 , H01L21/76251
摘要： A method including a phosphorous ion introduction step for implanting phosphorous ions from a side of a surface Si layer into an SOI substrate in which the surface Si layer and an embedded oxide layer having a predetermined thickness are formed on an Si base material layer to convert the embedded oxide layer into a PSG layer to lower a softening point. An SiC forming step is performed by heating the SOI substrate having the PSG layer formed therein in an atmosphere of hydrocarbon-based gas to convert the surface Si layer into SiC. Thereafter, the resulting substrate is cooled to form a single crystal SiC layer on a surface thereof.
摘要翻译：一种包括磷离子引入步骤的方法，用于将磷离子从表面Si层的一侧注入到其中表面Si层和具有预定厚度的嵌入氧化物层的SOI衬底形成在Si基材层上，以将将氧化物嵌入PSG层以降低软化点。通过在烃类气体的气氛中加热其中形成有PSG层的SOI衬底以将表面Si层转化为SiC来进行SiC形成步骤。此后，将所得衬底冷却以在其表面上形成单晶SiC层。

17. 发明授权

US07084049B2 Manufacturing method for buried insulating layer-type semiconductor silicon carbide substrate 有权
标题翻译：埋层绝缘层型半导体碳化硅基板的制造方法
公开(公告)号：US07084049B2
公开(公告)日：2006-08-01
申请号：US10351385
申请日：2003-01-27
申请人： Katsutoshi Izumi , Motoi Nakao , Yoshiaki Ohbayashi , Keiji Mine , Seisaku Hirai , Fumihiko Jobe , Tomoyuki Tanaka
发明人： Katsutoshi Izumi , Motoi Nakao , Yoshiaki Ohbayashi , Keiji Mine , Seisaku Hirai , Fumihiko Jobe , Tomoyuki Tanaka
IPC分类号： H01L21/20 , H01L21/36 , C30B23/00 , C30B25/00 , C30B28/12
CPC分类号： H01L21/7624 , H01L21/02378 , H01L21/02381 , H01L21/02488 , H01L21/02529 , H01L21/02532 , H01L21/02639 , H01L21/02656 , H01L21/0445 , H01L21/7602 , H01L21/76251
摘要： A manufacturing method for a buried insulating layer-type semiconductor silicon carbide substrate comprises the step of placing an SOI substrate 100, which has a surface silicon layer 130 of a predetermined thickness and a buried insulator 120, in a heating furnace 200 and of increasing the temperature of the atmosphere within heating furnace 200 while supplying a mixed gas (G1+G2) of a hydrogen gas G1 and of a hydrocarbon gas G2 into heating furnace 200, thereby, of metamorphosing surface silicon layer 130 of SOI substrate 100 into a single crystal silicon carbide thin film 140.
摘要翻译：掩埋绝缘层型半导体碳化硅衬底的制造方法包括将具有预定厚度的表面硅层130和掩埋绝缘体120的SOI衬底100放置在加热炉200中的步骤，同时向加热炉200供给氢气G 1和烃气G 2的混合气体（G 1 + G 2），从而将SOI衬底100的变形表面硅层130 成为单晶碳化硅薄膜140。

18. 发明授权

US5459347A Method of making field-effect semiconductor device on SOI 失效
标题翻译：在SOI上制作场效应半导体器件的方法
公开(公告)号：US5459347A
公开(公告)日：1995-10-17
申请号：US355110
申请日：1994-12-13
申请人： Yasuhisa Omura , Katsutoshi Izumi
发明人： Yasuhisa Omura , Katsutoshi Izumi
IPC分类号： H01L21/336 , H01L29/786 , H01L29/78 , H01L33/00
CPC分类号： H01L29/66772 , H01L29/78651
摘要： A field-effect semiconductor device of this invention includes a first insulating film formed on a semiconductor substrate, a source region of a second conductivity type and a drain region of the second conductivity type, which are arranged on the insulating film and are formed on both the sides of a semiconductor active layer of a first conductivity type, a second insulating film for covering the top and side surfaces of the semiconductor active layer, the source region, and the drain region, a gate electrode arranged on the second insulating film corresponding to the semiconductor active layer, a non-oxidizable third insulating film arranged on the second insulating film for covering the side surfaces of the semiconductor active layer and the source and drain regions, and the other regions, a fourth insulating film arranged on the non-oxidizable third insulating film, a fifth insulating film for covering a portion of the third insulating film located on the side surfaces of the source and drain regions, the fourth insulating film, the semiconductor active layer, the second insulating film arranged on the top surfaces of the source and drain regions, and a gate electrode arranged on the second insulating film, and a source electrode and a drain electrode arranged on the fifth insulating film and connected to the source region and the drain region, respectively, through contact holes formed in the fifth insulating film and the second insulating film.
摘要翻译：本发明的场效应半导体器件包括形成在半导体衬底上的第一绝缘膜，第二导电类型的源极区和第二导电类型的漏极区，它们布置在绝缘膜上并形成在两者上第一导电类型的半导体有源层的侧面，用于覆盖半导体有源层，源极区域和漏极区域的顶表面和侧表面的第二绝缘膜，布置在对应于第二绝缘膜的第二绝缘膜上的栅电极所述半导体活性层，布置在所述第二绝缘膜上用于覆盖所述半导体有源层和源极和漏极区域的侧表面的不可氧化的第三绝缘膜和其它区域，布置在不可氧化的第四绝缘膜上的第四绝缘膜第三绝缘膜，用于覆盖位于所述源的侧表面上的所述第三绝缘膜的一部分的第五绝缘膜 e和漏极区域，第四绝缘膜，半导体有源层，布置在源极和漏极区域的顶表面上的第二绝缘膜，以及布置在第二绝缘膜上的栅电极，以及源电极和漏电极配置在第五绝缘膜上，分别通过形成在第五绝缘膜和第二绝缘膜中的接触孔连接到源极区域和漏极区域。

19. 发明授权

US5188973A Method of manufacturing SOI semiconductor element 失效
标题翻译：制造SOI半导体元件的方法
公开(公告)号：US5188973A
公开(公告)日：1993-02-23
申请号：US877446
申请日：1992-04-30
申请人： Yasuhisa Omura , Yasuo Kunii , Katsutoshi Izumi
发明人： Yasuhisa Omura , Yasuo Kunii , Katsutoshi Izumi
IPC分类号： H01L27/12 , H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/78645 , H01L29/78648 , H01L29/78654
摘要： According to a method of manufacturing an SOI semiconductor element of this invention, a structure obtained by forming a first semiconductor layer on a first insulator is prepared. A process mask is arranged on the first semiconductor layer. The process mask has a groove pattern of a predetermined size. A groove extending between the first semiconductor layer and the first insulator layer is formed by etching the first semiconductor layer on the basis of the groove pattern of the process mask to expose the first insulator layer and etching the first insulator layer to a predetermined depth. A second semiconductor layer serving as a buried electrode is formed in the groove such that a level of an upper surface of the second semiconductor layer is equal to a level of a bottom surface of the first semiconductor layer. A second insulator layer is formed on the second semiconductor layer. Crystalline growth of a semiconductor layer is performed from side surfaces of the groove to bury the groove with a monocrystalline semiconductor. A source region and a drain region are formed in the monocrystalline semiconductor buried in the groove. A gate electrode is formed on the monocrystalline semiconductor through a gate oxide film.
摘要翻译：根据本发明的SOI半导体元件的制造方法，准备在第一绝缘体上形成第一半导体层而获得的结构。处理掩模布置在第一半导体层上。处理掩模具有预定尺寸的凹槽图案。通过基于处理掩模的凹槽图案蚀刻第一半导体层来形成在第一半导体层和第一绝缘体层之间延伸的凹槽，以暴露第一绝缘体层并将第一绝缘体层蚀刻到预定深度。用作掩埋电极的第二半导体层形成在沟槽中，使得第二半导体层的上表面的电平等于第一半导体层的底表面的电平。在第二半导体层上形成第二绝缘体层。从槽的侧面进行半导体层的结晶生长，以用单晶半导体填埋槽。源极区域和漏极区域形成在埋入槽中的单晶半导体中。栅电极通过栅极氧化膜形成在单晶半导体上。

20. 发明授权

US5040043A Power semiconductor device 失效
标题翻译：功率半导体器件
公开(公告)号：US5040043A
公开(公告)日：1991-08-13
申请号：US420185
申请日：1989-10-12
申请人： Terukaza Ohno , Katsutoshi Izumi
发明人： Terukaza Ohno , Katsutoshi Izumi
IPC分类号： H01L21/8249 , H01L21/76 , H01L21/822 , H01L27/04 , H01L27/06 , H01L27/088 , H01L27/10 , H01L29/78 , H01L29/786
CPC分类号： H01L29/78648 , H01L21/8221 , H01L27/0623 , H01L27/0688 , H01L27/088 , H01L29/78654
摘要： A power semiconductor device includes a layered first insulating region (101) formed on a first major surface of a semiconductor layer (58), a first conductive layer (104, 105, 106, 107, 108, 109) formed on the first insulating region and having the same conductivity type as that of the semiconductor layer, a layered second insulating region (100) formed on the first conductive layer, a vertical power transistor (A) having the semiconductor layer as one of its components and formed on the first major surface of the semiconductor layer, a third insulating region (102) for dielectrically isolating the first conductive layer from the other conductive layer, and a control MIS transistor (B, C), formed on the second insulating region, for controlling the vertical power transistor. A predetermined bias is applied on the first conductive layer to prevent formation of a back channel of the control MIS transistor.

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