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11. 发明授权

US09818493B2 Memory device, memory system, and method for operating memory device 有权
公开(公告)号：US09818493B2
公开(公告)日：2017-11-14
申请号：US14469159
申请日：2014-08-26
申请人： SK hynix Inc.
发明人： Dong-Uk Lee
IPC分类号： G11C29/36 , G11C29/38 , G11C29/10 , G11C29/26
CPC分类号： G11C29/36 , G11C29/10 , G11C29/26 , G11C2029/2602
摘要： A memory device includes a first memory block suitable for transmitting and receiving signals through a first channel, a second memory block suitable for transmitting and receiving signals through a second channel, and a test control unit suitable for applying a first command signal among a plurality of command signals to the first and second channels at different values, while applying the plurality of command signals from an exterior of the memory device to the first and second channels in a test operation, wherein the first command signal distinguishes write and read operations of the first and second memory blocks, wherein, when the first memory block performs a read operation in the test operation, the second memory block performs a write operation, and data outputted from the first memory block is inputted to the second memory block.

12. 发明授权

US09646664B2 Memory device and memory system including the same 有权
公开(公告)号：US09646664B2
公开(公告)日：2017-05-09
申请号：US15149989
申请日：2016-05-09
申请人： SK hynix Inc.
发明人： Young-Ju Kim , Dong-Uk Lee
IPC分类号： G11C8/18 , G11C8/12 , G11C11/408 , G11C11/406
CPC分类号： G11C8/18 , G11C8/12 , G11C11/40618 , G11C11/4087
摘要： A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column.

13. 发明授权

US09552255B2 Memory device with parallel odd and even column access and methods thereof 有权
标题翻译：具有并行奇数和偶数列访问的存储器件及其方法
公开(公告)号：US09552255B2
公开(公告)日：2017-01-24
申请号：US14926834
申请日：2015-10-29
申请人： SK hynix Inc.
发明人： Kyung-Whan Kim , Dong-Uk Lee
IPC分类号： G06F11/10 , G11C7/10 , G11C7/22 , G11C8/18
CPC分类号： G06F11/1048 , G11C7/1018 , G11C7/1042 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C8/12 , G11C8/18 , G11C2207/005 , G11C2207/2281 , G11C2207/229
摘要： A memory device includes: a plurality of first lines; a plurality of second lines; a plurality of bank groups each including a predetermined number of banks; and a column signal transmission unit suitable for transmitting one or more column command signals and one or more column address signals to the bank groups through the first lines based on an odd-numbered column command, and transmitting the column command signals and the column address signals to the bank groups through the second lines based on an even-numbered column command.
摘要翻译：存储装置包括：多条第一线; 多条第二线; 多个银行组，每个银行组包括预定数量的银行; 以及列信号发送单元，其适于基于奇数列命令通过第一线路将一个或多个列命令信号和一个或多个列地址信号发送到组组，并且发送列命令信号和列地址信号根据偶数列命令通过第二行向银行组发送。

14. 发明授权

US09368175B2 Semiconductor memory device receiving multiple commands simultaneously and memory system including the same 有权
标题翻译：同时接收多个命令的半导体存储器件和包括其的存储器系统
公开(公告)号：US09368175B2
公开(公告)日：2016-06-14
申请号：US14493026
申请日：2014-09-22
申请人： SK hynix Inc.
发明人： Dong-Uk Lee
IPC分类号： G11C8/18 , G11C7/22 , G11C8/12
CPC分类号： G11C8/18 , G11C7/22 , G11C8/12
摘要： A semiconductor memory device may include: a memory cell array; a first address controller configured to receive a first command and a first address and generate a first control signal in response to the first command; and a second address controller configured to receive a second address and a second command inputted at the same time as the first command, and generate a second control signal in response to the second command.
摘要翻译：半导体存储器件可以包括：存储单元阵列; 第一地址控制器，被配置为接收第一命令和第一地址，并响应于所述第一命令产生第一控制信号; 以及第二地址控制器，被配置为接收与第一命令同时输入的第二地址和第二命令，并且响应于第二命令生成第二控制信号。

15. 发明授权

US09275703B2 Semiconductor integrated circuit with stack package structure 有权
标题翻译：半导体集成电路采用堆叠封装结构
公开(公告)号：US09275703B2
公开(公告)日：2016-03-01
申请号：US13719096
申请日：2012-12-18
申请人： SK hynix Inc.
发明人： Dong-Uk Lee , Young-Ju Kim , Keun-Soo Song
IPC分类号： G11C7/00 , G11C7/22 , G11C8/18 , G11C7/10
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1012 , G11C7/1039 , G11C7/1042 , G11C7/1054 , G11C7/1081 , G11C7/12 , G11C7/22 , G11C8/18 , G11C2207/107
摘要： A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.
摘要翻译：一种半导体集成电路，包括垂直堆叠的第一半导体芯片和第二半导体芯片，其中，所述第一半导体芯片包括第一列数据驱动电路，其被配置为以基于以下的DDR（双倍数据速率）方案将内部数据传输到所述第二半导体芯片内部选通信号和第一列选通信号驱动电路，被配置为基于内部选通信号产生与由第一列数据驱动电路发送到第二半导体芯片的第一列数据源同步的第一列选通信号，并将第一列选通信号发送到第二半导体芯片。

16. 发明授权

US10761132B2 Integrated circuit chip and semiconductor device including the same 有权
公开(公告)号：US10761132B2
公开(公告)日：2020-09-01
申请号：US16199297
申请日：2018-11-26
申请人： SK hynix Inc.
发明人： Dong-Uk Lee
IPC分类号： G01R31/28 , H01L25/065 , H01L25/18 , H01L23/48
摘要： A semiconductor device includes a first integrated chip; a second integrated chip; a plurality of reference through-chip vias formed through the first and second integrated circuit chips; and at least a normal through-chip via formed through the first and second integrated circuit chips, wherein the first integrated circuit chip comprises: a plurality of reference sourcing circuits suitable for sourcing a reference current to the respective reference through-chip vias; and at least a sourcing circuit suitable for sourcing the reference current to the normal through-chip via, and wherein the second integrated circuit chip comprises: a plurality of reference sinking circuits suitable for sinking currents flowing through the respective reference through-chip vias; a line suitable for electrically coupling the plurality of reference through-chip vias; a comparison voltage generation circuit suitable for generating a plurality of comparison voltages based on a voltage of the line; at least a sinking circuit suitable for sinking a current flowing through the normal through-chip via; and a comparison circuit suitable for comparing the voltage of the normal through-chip via to the plurality of comparison voltages.

17. 发明授权

US10255957B2 Semiconductor integrated circuit 有权
公开(公告)号：US10255957B2
公开(公告)日：2019-04-09
申请号：US15678634
申请日：2017-08-16
申请人： SK hynix Inc.
发明人： Dong-Uk Lee , Young-Ju Kim , Keun-Soo Song
IPC分类号： G11C7/22 , G11C8/18 , G11C7/10 , G11C7/12
摘要： A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

18. 发明授权

US09773535B2 Semiconductor integrated circuit including at least one master chip and at least one slave chip 有权
公开(公告)号：US09773535B2
公开(公告)日：2017-09-26
申请号：US15004060
申请日：2016-01-22
申请人： SK hynix Inc.
发明人： Dong-Uk Lee , Young-Ju Kim , Keun-Soo Song
IPC分类号： G11C7/00 , G11C7/22 , G11C8/18 , G11C7/10 , G11C7/12
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1012 , G11C7/1039 , G11C7/1042 , G11C7/1054 , G11C7/1081 , G11C7/12 , G11C7/22 , G11C8/18 , G11C2207/107
摘要： A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

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