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11. 发明授权

US09583539B2 Word line connection for memory device and method of making thereof 有权
标题翻译：用于存储器件的字线连接及其制造方法
公开(公告)号：US09583539B2
公开(公告)日：2017-02-28
申请号：US14463113
申请日：2014-08-19
申请人： SanDisk 3D LLC
发明人： Seje Takaki
IPC分类号： H01L27/24 , H01L21/768 , H01L21/3213 , H01L27/115 , H01L27/06 , H01L45/00
CPC分类号： H01L27/2481 , H01L21/32139 , H01L21/76892 , H01L27/0688 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L45/1226 , H01L45/141 , H01L45/145 , H01L45/149 , H01L45/16
摘要： A three-dimensional monolithic memory device includes at least one device region and a plurality of contact regions each including a stack of an alternating plurality of conductive word line contact layers and insulating layers located over a substrate, where the stacks in the plurality of contact regions are separated from one another by an insulating material, and a bridge connector including a conductive material extending between a first conductive word line contact layer of a first stack in a first contact region and a second conductive word line contact layer of a second stack in a second contact region, where the first word line contact layer extends in a first contact level substantially parallel to a major surface of the substrate and the second word line contact layer extends in a second contact level substantially parallel to the major surface of the substrate that is different than the first level.
摘要翻译：三维单片存储器件包括至少一个器件区域和多个接触区域，每个接触区域包括交替的多个导电字线接触层和位于衬底上的绝缘层的堆叠，其中多个接触区域中的堆叠通过绝缘材料彼此分离，并且桥连接器包括在第一接触区域中的第一堆叠体的第一导电字线接触层和第二层叠体的第二导电字线接触层之间延伸的导电材料第二接触区域，其中第一字线接触层在基本上平行于衬底的主表面的第一接触电平中延伸，而第二字线接触层在基本上平行于衬底的主表面的第二接触电平中延伸，不同于第一级。

12. 发明申请

US20160247859A1 Floating Staircase Word Lines and Process in a 3D Non-Volatile Memory Having Vertical Bit Lines 有权
标题翻译：浮动楼梯字线和具有垂直位线的3D非易失性存储器中的过程
公开(公告)号：US20160247859A1
公开(公告)日：2016-08-25
申请号：US14631616
申请日：2015-02-25
申请人： SanDisk 3D LLC
发明人： Seje Takaki
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L23/528 , G11C5/025 , G11C5/06 , G11C5/063 , G11C16/08 , H01L21/31111 , H01L21/76802 , H01L21/76837 , H01L21/76877 , H01L21/76895 , H01L27/1052 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L27/2481 , H01L27/249 , H01L45/122 , H01L45/16
摘要： A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2D array of vertical bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers and traverses the plurality of memory layers with a segment in each memory layer. The plurality of staircase word lines have their segments lined up to form a 2D array of stacks of segments. Riser for a pair of segments from each adjacent stacks at different memory layers is provided by a conductive sidewall layer of a stairwell disposed between the adjacent stacks. Multiple insulated conductive sidewall layers provide multiple risers for the adjacent stacks. Layer-by-layer stairwell excavation and sidewall processes between adjacent stacks create risers for different pairs of segments between stacks to form the staircase word lines.
摘要翻译： 3D非易失性存储器具有以三维图案布置的存储元件，其中堆叠在半导体衬底上的多个存储层。它具有垂直位线的2D阵列和多个阶梯字线。每个阶梯字线具有一系列交替的段和立管，并且在每个存储层中遍历多个存储层与段。多个阶梯字线将它们的片段排列成形成片段的二维阵列。用于来自不同存储器层处的每个相邻堆叠的一对段的提升器由设置在相邻堆叠之间的楼梯间隔器的导电侧壁层提供。多个绝缘导电侧壁层为相邻堆叠提供多个立管。相邻堆叠之间的逐层楼梯井开挖和侧壁过程在堆叠之间产生用于不同对的段的立管，以形成楼梯字线。

13. 发明申请

US20160141334A1 MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS WITH STAGGERED VERTICAL BIT LINE SELECT TRANSISTORS AND METHODS THERFOR 有权
标题翻译：具有STAGGERED垂直位线选择晶体管的单个三维存储器阵列及其方法
公开(公告)号：US20160141334A1
公开(公告)日：2016-05-19
申请号：US14542213
申请日：2014-11-14
申请人： SanDisk 3D LLC
发明人： Seje Takaki , Yoshio Mori
IPC分类号： H01L27/24 , G11C13/00
CPC分类号： H01L27/249 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0069 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： A monolithic three-dimensional memory array is provided that includes a plurality of global bit lines disposed above a substrate, each global bit line having a long axis, a plurality of vertically-oriented bit lines disposed above the global bit lines, a plurality of word lines disposed above the global bit lines, a plurality of memory cells coupled between the vertically-oriented bit lines and the word lines, and a plurality of vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines, each vertically-oriented bit line select transistor comprising a width and a thickness. Vertically-oriented bit line select transistors disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines. The width of each vertically-oriented bit line select transistor is greater than the thickness of the vertically-oriented bit line select transistors.
摘要翻译：提供了一种单片三维存储器阵列，其包括设置在衬底上方的多个全局位线，每个全局位线具有长轴，设置在全局位线上方的多个垂直取向的位线，多个字设置在全局位线之上的线，耦合在垂直取向的位线和字线之间的多个存储单元，以及耦合在垂直取向的位线和全局位线之间的多个垂直取向的位线选择晶体管每个垂直取向的位线选择晶体管包括宽度和厚度。设置在相邻全局位线之上的垂直取向的位线选择晶体管沿着全局位线的长轴的方向彼此偏移。每个垂直取向的位线选择晶体管的宽度大于垂直取向的位线选择晶体管的厚度。

14. 发明授权

US09343507B2 Dual channel vertical field effect transistor including an embedded electrode 有权
标题翻译：双通道垂直场效应晶体管包括一个嵌入式电极
公开(公告)号：US09343507B2
公开(公告)日：2016-05-17
申请号：US14206196
申请日：2014-03-12
申请人： SanDisk 3D LLC
发明人： Seje Takaki
IPC分类号： H01L29/76 , H01L27/24 , H01L29/78 , H01L29/66 , H01L27/115 , H01L29/788 , H01L27/112 , H01L29/792 , H01L29/423 , H01L29/10 , H01L45/00 , H01L29/49
CPC分类号： H01L27/2481 , H01L27/11273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L29/1033 , H01L29/42356 , H01L29/4925 , H01L29/4983 , H01L29/66666 , H01L29/7827 , H01L29/7889 , H01L29/7926 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： A device is disclosed including one or more field effect transistors, each field effect transistor including: an elongated drain contact line including an electrically conductive material extending along a first horizontal direction; a drain including a first conductivity type semiconductor region overlaying the drain contact line; a source including a the first conductivity type semiconductor region located above the drain; and a gate extending vertically between the drain and the source. Each field effect transistor may include a first channel and a second channel, each including a second conductivity type
摘要翻译：公开了一种包括一个或多个场效应晶体管的器件，每个场效应晶体管包括：细长的漏极接触线，包括沿着第一水平方向延伸的导电材料; 漏极，包括覆盖所述漏极接触线的第一导电类型半导体区域; 源极，包括位于漏极上方的第一导电类型半导体区域; 以及在漏极和源极之间垂直延伸的栅极。每个场效应晶体管可以包括第一通道和第二通道，每个通道包括第二导电类型

15. 发明授权

US09230905B2 Trench multilevel contact to a 3D memory array and method of making thereof 有权
标题翻译：与3D存储器阵列的沟槽多层接触及其制造方法
公开(公告)号：US09230905B2
公开(公告)日：2016-01-05
申请号：US14150162
申请日：2014-01-08
申请人： SanDisk 3D LLC
发明人： Seje Takaki , Michiaki Sano , Zhen Chen
IPC分类号： H01L23/50 , H01L27/24 , H01L27/115 , H01L21/768 , H01L27/06
CPC分类号： H01L23/50 , H01L21/768 , H01L21/76838 , H01L21/76877 , H01L27/0688 , H01L27/115 , H01L27/11519 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L27/2481 , H01L27/249 , H01L29/42332 , H01L29/7889 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A multilevel device includes: at least one device region and at least one contact region having a stack of alternating plurality of continuous electrically conductive layers and plurality of electrically insulating layers located over a base. Each electrically conductive layer in the stack is electrically insulated from the other electrically conductive layers in the stack. The base may include a raised portion and a plurality of recesses in the raised portion, each recess in the plurality of recesses having a different lateral size from the other recesses in the plurality of recesses. The electrically conductive layers in the stack may be substantially conformal to the plurality of recesses in the base and expose one or more top surfaces of the raised portion of the base. A first electrically conductive layer in the stack may be a topmost layer in a laterally central portion of a first one of the plurality of recesses. A second electrically conductive layer in the stack different from the first electrically conductive layer may be a topmost layer in a laterally central portion of a second one of the plurality of recesses.
摘要翻译：多电平装置包括：至少一个器件区域和至少一个接触区域，其具有交替的多个连续导电层和位于基极之上的多个电绝缘层的叠层。堆叠中的每个导电层与堆叠中的其它导电层电绝缘。基部可以包括凸起部分中的凸起部分和多个凹部，多个凹部中的每个凹部具有与多个凹部中的其它凹部不同的横向尺寸。堆叠中的导电层可以基本上与基座中的多个凹部共形并且露出基部的凸起部分的一个或多个顶表面。堆叠中的第一导电层可以是多个凹部中的第一个的横向中心部分中的最上层。不同于第一导电层的堆叠中的第二导电层可以是多个凹部中的第二导电层的横向中心部分中的最上层。

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