专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US09196373B2 Timed multiplex sensing 有权
标题翻译：定时复用传感
公开(公告)号：US09196373B2
公开(公告)日：2015-11-24
申请号：US14191130
申请日：2014-02-26
申请人： SANDISK 3D LLC
发明人： Anurag Nigam , Gopinath Balakrishnan
IPC分类号： G11C13/00 , G11C16/26 , G11C16/04 , G11C11/56
CPC分类号： G11C7/08 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75
摘要： Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.
摘要翻译：描述了使用检测方案来确定存储单元状态的方法，所述检测方案通过时间多路复用检测电路的部分来减少用于检测存储器单元的状态的检测电路的面积。读取操作可以包括预充电阶段，感测阶段和检测阶段。在一些实施例中，第一位线和第二位线可以并行地预充电到读取电压，然后可以串行地使用对应于第一位线和第二位线的所选存储单元的感测和/或检测相同的检测电路通过对检测电路的使用进行时间复用。在一些情况下，时间复用检测电路可以用于检测在读操作期间被感测到的两个或多个存储器单元相对应的两个或多个状态。

12. 发明申请

US20150243362A1 TIMED MULTIPLEX SENSING 有权
标题翻译：定时多传感器
公开(公告)号：US20150243362A1
公开(公告)日：2015-08-27
申请号：US14191130
申请日：2014-02-26
申请人： SANDISK 3D LLC
发明人： Anurag Nigam , Gopinath Balakrishnan
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C7/08 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75
摘要： Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.
摘要翻译：描述了使用检测方案来确定存储单元状态的方法，所述检测方案通过时间多路复用检测电路的部分来减少用于检测存储器单元的状态的检测电路的面积。读取操作可以包括预充电阶段，感测阶段和检测阶段。在一些实施例中，第一位线和第二位线可以并行地预充电到读取电压，然后可以串行地使用对应于第一位线和第二位线的所选存储单元的感测和/或检测相同的检测电路通过对检测电路的使用进行时间复用。在一些情况下，时间复用检测电路可以用于检测在读操作期间被感测到的两个或多个存储器单元相对应的两个或多个状态。

13. 发明申请

US20150106554A1 Regrouping and Skipping Cycles in Non-Volatile Memory 有权
标题翻译：在非易失性存储器中重新组合和跳过循环
公开(公告)号：US20150106554A1
公开(公告)日：2015-04-16
申请号：US14515387
申请日：2014-10-15
申请人： SanDisk 3D LLC
发明人： Gopinath Balakrishnan
IPC分类号： G11C16/10 , G06F12/02
CPC分类号： G11C16/107 , G06F12/0246 , G06F2212/7208 , G11C7/1006 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2213/71
摘要： A non-volatile memory system utilizes multiple programming cycles to write units of data, such as a logical page of data, to a non-volatile memory array. User data is evaluated before writing to determine whether programming can be skipped for bay addresses. The system determines whether programming can be skipped for an initial set of bay groups. If a bay group cannot be skipped, the system determines whether the bay group includes individual bays that may be skipped. Bays are regrouped into new bay groups to reduce the number of BAD cycles during programming. Independent column addressing for multiple bays within a bay group is provided. During a column address cycle, a separate column address is provided to the bays to select different columns for programming within each bay. By simultaneously programming multiple column addresses during a single column address cycle, the system may skip programming for some column address cycles.
摘要翻译：非易失性存储器系统利用多个编程周期将诸如数据的逻辑页面的数据单元写入非易失性存储器阵列。用户数据在写入前进行评估，以确定是否可以跳过槽位地址的编程。系统确定是否可以跳过最初的一组托架组的编程。如果无法跳过托架组，系统将确定托架组是否包括可跳过的单独托架。海湾重新组合成新的海湾组，以减少编程期间的BAD周期数。提供了一个独立的列寻址，用于一个托架组中的多个托架。在列地址周期中，单独的列地址提供给托架，以在每个托架中选择不同的列进行编程。通过在单个列地址周期期间同时编程多个列地址，系统可能会跳过某些列地址周期的编程。

14. 发明授权

US08947972B2 Dynamic address grouping for parallel programming in non-volatile memory 有权
标题翻译：非易失性存储器中并行编程的动态地址分组
公开(公告)号：US08947972B2
公开(公告)日：2015-02-03
申请号：US13839300
申请日：2013-03-15
申请人： SanDisk 3D LLC
发明人： Gopinath Balakrishnan , Tz-Yi Liu
IPC分类号： G11C8/18 , G06F12/02
CPC分类号： G06F12/0246 , G11C7/1006 , G11C13/0007 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2213/71
摘要： A non-volatile memory system evaluates user data before writing in order to potentially group addresses for writing within a cycle. The system can determine which sense amplifier addresses of a column address will be programmed in a column address cycle. The number of bits that will be programmed is compared with an allowable number of parallel bits. The system generates groups of sense amplifier addresses based on the comparison. The system generates groups that include a total number of bits to be programmed that is within the allowable number of parallel bits. Each group is programmed in one sense amplifier address cycle. Multiple sense amplifier addresses can be grouped for programming while still remaining within an allowable number of parallel programming bits. The system performs a read before write operation and generates bitmap data for the grouping information corresponding sense amplifier addresses.
摘要翻译：非易失性存储器系统在写入之前评估用户数据，以便在一个周期内潜在的组地址进行写入。该系统可以确定在列地址周期中将编程列地址的哪个读出放大器地址。将编程的位数与允许的并行位数进行比较。该系统基于比较产生一组读出放大器地址。系统生成组，其中包括要编程的总位数在允许的并行位数内。每组在一个读出放大器地址周期中进行编程。多个读出放大器地址可以分组编程，同时仍然保留在允许的并行编程位数中。该系统在写入操作之前进行读取，并产生对应读出放大器地址的分组信息的位图数据。

15. 发明授权

US08947944B2 Program cycle skip evaluation before write operations in non-volatile memory 有权
标题翻译：在非易失性存储器中进行写操作之前的程序循环跳过评估
公开(公告)号：US08947944B2
公开(公告)日：2015-02-03
申请号：US13839366
申请日：2013-03-15
申请人： SanDisk 3D LLC
发明人： Gopinath Balakrishnan , Tz-Yi Liu , Henry Zhang
IPC分类号： G11C7/10 , G11C7/06
CPC分类号： G11C7/06 , G11C7/1006 , G11C7/1087 , G11C13/0061 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2213/71
摘要： A non-volatile memory system is disclosed that evaluates during a read before write operation whether to skip programming of portions of group of memory cells during a subsequent write operation. By evaluating skip information during a read before write operation, the write operation can be expedited. The additional overhead for evaluating skip information is consumed during the read before write operation. By performing a skip evaluation during the read before write operation, a full analysis of the availability of skipping programming for memory cells can be performed. Skip evaluations in different embodiments may be performed for entire bay address cycles, column address cycles, and/or sense amplifier address cycles. In some embodiments, some skip evaluations are performed during read before write operations while others are deferred to the write operation. In this manner, the number of data latches for storing skip information can be decreased.
摘要翻译：公开了一种非易失性存储器系统，其在写操作期间的读取期间评估是否在随后的写入操作期间跳过存储器单元组的部分的编程。通过在写入操作期间读取期间评估跳过信息，可以加速写入操作。用于评估跳过信息的额外开销在写入操作期间被读取。通过在写操作期间执行跳过评估，可以执行对存储器单元的跳过编程的可用性的全面分析。可以在整个托架地址周期，列地址周期和/或读出放大器地址周期中执行不同实施例中的跳过评估。在一些实施例中，在写入操作期间的读取期间执行一些跳过评估，而其他跳过评估被推迟到写入操作。以这种方式，可以减少用于存储跳过信息的数据锁存器的数量。

16. 发明申请

US20140269106A1 Program Cycle Skip Evaluation Before Write Operations In Non-Volatile Memory 有权
标题翻译：在非易失性存储器中写入操作之前的程序循环跳过评估
公开(公告)号：US20140269106A1
公开(公告)日：2014-09-18
申请号：US13839366
申请日：2013-03-15
申请人： SANDISK 3D LLC
发明人： Gopinath Balakrishnan , Tz-Yi Liu , Henry Zhang
IPC分类号： G11C7/06 , G11C7/10
CPC分类号： G11C7/06 , G11C7/1006 , G11C7/1087 , G11C13/0061 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2213/71
摘要： A non-volatile memory system is disclosed that evaluates during a read before write operation whether to skip programming of portions of group of memory cells during a subsequent write operation. By evaluating skip information during a read before write operation, the write operation can be expedited. The additional overhead for evaluating skip information is consumed during the read before write operation. By performing a skip evaluation during the read before write operation, a full analysis of the availability of skipping programming for memory cells can be performed. Skip evaluations in different embodiments may be performed for entire bay address cycles, column address cycles, and/or sense amplifier address cycles. In some embodiments, some skip evaluations are performed during read before write operations while others are deferred to the write operation. In this manner, the number of data latches for storing skip information can be decreased.
摘要翻译：公开了一种非易失性存储器系统，其在写操作期间的读取期间评估是否在随后的写入操作期间跳过存储器单元组的部分的编程。通过在写入操作期间读取期间评估跳过信息，可以加速写入操作。用于评估跳过信息的额外开销在写入操作期间被读取。通过在写操作期间执行跳过评估，可以执行对存储器单元的跳过编程的可用性的全面分析。可以在整个托架地址周期，列地址周期和/或读出放大器地址周期中执行不同实施例中的跳过评估。在一些实施例中，在写入操作期间的读取期间执行一些跳过评估，而其他跳过评估被推迟到写入操作。以这种方式，可以减少用于存储跳过信息的数据锁存器的数目。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式