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11. 发明申请

US20080244242A1 Using a Register File as Either a Rename Buffer or an Architected Register File 审中-公开
标题翻译：使用注册文件作为重命名缓冲区或建筑注册表文件
公开(公告)号：US20080244242A1
公开(公告)日：2008-10-02
申请号：US11695303
申请日：2007-04-02
申请人： Christopher M. Abernathy , William E. Burky , Joel A. Silberman
发明人： Christopher M. Abernathy , William E. Burky , Joel A. Silberman
IPC分类号： G06F7/38
CPC分类号： G06F9/30123 , G06F9/3013 , G06F9/384 , G06F9/3851 , G06F9/3853 , G06F9/3857 , G06F9/3885
摘要： A computer implemented method, apparatus, and computer usable program code are provided for implementing a set of architected register files as a set of temporary rename buffers. An instruction dispatch unit receives an instruction that includes instruction data. The instruction dispatch unit determines a thread mode under which a processor is operating. Responsive to determining the thread mode, the instruction dispatch unit determines an ability to use the set of architected register files as the set of temporary rename buffers. Responsive to the ability to use the set of architected register files as the set of temporary rename buffers, the instruction dispatch unit analyzes the instruction to determine an address of an architected register file in the set of architected register files where the instruction data is to be stored. The architected register file operating as a temporary rename buffer stores the instruction data as finished data.
摘要翻译：提供了一种计算机实现的方法，装置和计算机可用程序代码，用于将一组架构化的寄存器文件实现为一组临时重命名缓冲器。指令分配单元接收包括指令数据的指令。指令调度单元确定处理器在其下操作的线程模式。响应于确定线程模式，指令分派单元确定使用一组架构化寄存器文件作为临时重命名缓冲器集合的能力。响应于使用该组建筑寄存器文件作为一组临时重命名缓冲器的能力，指令分派单元分析该指令以确定在该指令数据将被设置的一组架构化寄存器文件集中的架构化寄存器文件的地址存储。作为临时重命名缓冲区运行的架构化寄存器文件将指令数据存储为完成的数据。

12. 发明申请

US20080016324A1 Method And Apparatus For Register Renaming Using Multiple Physical Register Files And Avoiding Associative Search 失效
标题翻译：使用多个物理寄存器文件进行寄存器重命名的方法和装置，并避免关联搜索
公开(公告)号：US20080016324A1
公开(公告)日：2008-01-17
申请号：US11456878
申请日：2006-07-12
申请人： William E. Burky , Krishnan K. Kailas , Balaram Sinharoy
发明人： William E. Burky , Krishnan K. Kailas , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/384
摘要： A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming scheme at the instruction dispatch or wake-up/issue time.
摘要翻译：一种用于使用多个物理寄存器文件来实现用于数字数据处理器的寄存器重命名方案的方法，所述多个物理寄存器文件用于支持来自一个或多个线程的多个指令的无序执行，所述方法包括：使用DEF表来存储使用指令标签的多条指令之间的指令依赖性，DEF表由逻辑寄存器名称索引，并且每个逻辑寄存器包括一个条目; 使用由指令标签索引的重命名USE表来存储由多个线程使用的多组不同类型的非构造的逻辑寄存器副本共享的逻辑到物理寄存器映射信息; 使用最后一个USE表将多组不同类型的非构造的逻辑寄存器副本的数据传输到第一组架构化的注册文件中，最后的USE表由第二组重命名的物理寄存器名称索引文件; 并在指令发送或唤醒/发出时间执行注册重命名方案。

13. 发明授权

US07194603B2 SMT flush arbitration 失效
标题翻译： SMT冲洗仲裁
公开(公告)号：US07194603B2
公开(公告)日：2007-03-20
申请号：US10422026
申请日：2003-04-23
申请人： William E. Burky , Hung Q. Le , Dung Q. Nguyen , David A. Schroter
发明人： William E. Burky , Hung Q. Le , Dung Q. Nguyen , David A. Schroter
IPC分类号： G06F9/30 , G06F9/44
CPC分类号： G06F9/3867 , G06F9/3851 , G06F9/3855 , G06F9/3861
摘要： A methodology to process flushes in an SMT processor with a dynamically shared group completion table (GCT) and a Flush table comprises identification of incoming flush sources by thread. This uses the forward link array by flush source to determine the next instruction group following the group indicated by the flush source (for example, for mispredicts and load/store flush-next type flushes). Presentation of flush completion table entry numbers or instruction group identifiers (Gtags) to the flush table for computation of oldest flushed group tag corresponding to each thread. The flush selection cycle wherein the flush table outputs are compared against saved versions of all the flush Gtags presented to determine which flush source matches the oldest group output from the flush table. The flush source information is used with the selected oldest Gtag to determine the appropriate additional flushing action to take during the flush cycle.
摘要翻译：使用动态共享组完成表（GCT）和冲洗表处理SMT处理器中的刷新的方法包括通过线程识别输入的刷新源。这通过flush源使用前向链接数组来确定闪存源指示的组之后的下一个指令组（例如，用于错误预测和加载/存储flush-next类型刷新）。将刷新完成表条目号或指令组标识符（Gtags）呈现给刷新表，以计算与每个线程相对应的最旧刷新组标签。将刷新表输出的刷新选择循环与所提供的所有刷新Gtags的保存版本进行比较，以确定哪个flush源与flush表中最早的组输出相匹配。冲洗源信息与所选最旧的Gtag一起使用，以确定在冲洗循环期间采取的适当的额外冲洗动作。

14. 发明授权

US06748493B1 Method and apparatus for managing memory operations in a data processing system using a store buffer 有权
标题翻译：一种使用存储缓冲器来管理数据处理系统中的存储器操作的方法和装置
公开(公告)号：US06748493B1
公开(公告)日：2004-06-08
申请号：US09201214
申请日：1998-11-30
申请人： Ronald Xavier Arroyo , William E. Burky , Jody Bern Joyner
发明人： Ronald Xavier Arroyo , William E. Burky , Jody Bern Joyner
IPC分类号： G06F1300
CPC分类号： G06F12/0835 , G06F13/1663 , G06F13/1673
摘要： A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory controller's store buffer and memory. The memory controller's store buffer is configured into one or more arrays sufficiently mapped to handle I/O and CPU bandwidth requirements. The combination of the store buffer and the control logic operates as a front end within the memory controller in that all memory requests are first processed by the control logic/store buffer combination for reducing memory latency and increasing effective memory bandwidth by eliminating certain memory read and write operations.
摘要翻译：共享存储器多处理器（SMP）数据处理系统包括实现在存储器控制器中的存储缓冲器，用于在数据处理系统内临时存储最近访问的存储器数据。存储器控制器包括用于维持存储器控制器的存储缓冲器和存储器之间的一致性的控制逻辑。存储器控制器的存储缓冲器被配置成一个或多个阵列，其被充分映射以处理I / O和CPU带宽要求。存储缓冲器和控制逻辑的组合作为存储器控制器中的前端操作，因为所有存储器请求首先由控制逻辑/存储缓冲器组合处理，以减少存储器延迟并通过消除某些存储器读取和增加有效的存储器带宽写操作。

15. 发明授权

US08495342B2 Configuring plural cores to perform an instruction having a multi-core characteristic 有权
标题翻译：配置多个内核以执行具有多核特性的指令
公开(公告)号：US08495342B2
公开(公告)日：2013-07-23
申请号：US12335921
申请日：2008-12-16
申请人： Louis B. Capps, Jr. , Michael J. Shapiro , Robert H. Bell, Jr. , Thomas E. Cook , William E. Burky
发明人： Louis B. Capps, Jr. , Michael J. Shapiro , Robert H. Bell, Jr. , Thomas E. Cook , William E. Burky
IPC分类号： G06F9/30
CPC分类号： G06F9/5061 , G06F9/3842 , G06F9/3851 , G06F9/3887
摘要： A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.
摘要翻译：具有多个核的处理器协调在核上执行的功能，以基于当前执行的软件的特性自动，动态地和重复地重新配置核以获得最佳性能。运行线程的核心检测线程的多核特性，并为线程分配一个或多个其他内核，以将内核动态组合到功能上相当于共同核心的内核，从而更有效地执行线程。

16. 发明授权

US08041928B2 Information handling system with real and virtual load/store instruction issue queue 有权
标题翻译：具有实际和虚拟加载/存储指令问题队列的信息处理系统
公开(公告)号：US08041928B2
公开(公告)日：2011-10-18
申请号：US12341930
申请日：2008-12-22
申请人： William E. Burky , Kurt A. Feiste , Dung Quoc Nguyen , Balaram Sinharoy , Albert Thomas Williams
发明人： William E. Burky , Kurt A. Feiste , Dung Quoc Nguyen , Balaram Sinharoy , Albert Thomas Williams
IPC分类号： G06F9/00
CPC分类号： G06F9/3834 , G06F9/3838 , G06F9/3851
摘要： An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real and virtual load/store instructions. Real load/store instructions execute in a load store unit LSU. Virtual load/store instructions are pending execution in the LSU. The LSU may keep track of each virtual load/store instruction within the issue queue by thread, type, and pointer data. Provided that all dependencies are clear for a pending virtual load/store instruction, the LSU marks the pending virtual load/store instruction as real. The pending virtual load/store instruction may then issue to the LSU as a real load/store instruction.
摘要翻译：信息处理系统包括可执行发布队列虚拟加载/存储指令操作的处理器。问题队列通过实际/虚拟依赖标志来维护加载和存储指令。问题队列为实际和虚拟加载/存储指令提供存储资源。实际加载/存储指令在加载存储单元LSU中执行。虚拟加载/存储指令正在等待在LSU中执行。 LSU可以通过线程，类型和指针数据跟踪发布队列内的每个虚拟加载/存储指令。假设所有依赖关系对待处理的虚拟加载/存储指令都是清楚的，则LSU将待处理的虚拟加载/存储指令标记为真实的。然后，挂起的虚拟加载/存储指令可以作为实际加载/存储指令发布到LSU。

17. 发明申请

US20100257341A1 Selective Execution Dependency Matrix 审中-公开
标题翻译：选择性执行依赖矩阵
公开(公告)号：US20100257341A1
公开(公告)日：2010-10-07
申请号：US12417801
申请日：2009-04-03
申请人： Mary D. Brown , James W. Bishop , William E. Burky , John B. Griswell, JR. , Dung Q. Nguyen , Todd A. Venton
发明人： Mary D. Brown , James W. Bishop , William E. Burky , John B. Griswell, JR. , Dung Q. Nguyen , Todd A. Venton
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a processor execution queue and each cell represents a dependency relationship between two instructions in the processor execution queue. A first latch couples to the first array and comprises a first bit, the first bit indicating a first status. A second latch couples to the first array and comprises a second bit, the second bit indicating a second status. A first read port couples to the first array, comprising a first read wordline and a first read bitline. The first read wordline couples to the first latch and a first column and asserts a first available signal based on the first bit. The first read bitline couples to a first row and generates a first ready signal based on the first available signal and a first cell. A second read port couples to the first array and comprises a second read wordline and a second read bitline. The second read wordline couples to the second latch and the first column and asserts a second available signal based on the second bit. The second read bitline couples to the first row and generates a second ready signal based on the second read wordline and the first cell.
摘要翻译：具有依赖矩阵的处理器包括第一阵列，其包括以多个列排列的多个单元和多个行。每行表示处理器执行队列中的指令，每个单元表示处理器执行队列中的两个指令之间的依赖关系。第一锁存器耦合到第一阵列并且包括第一位，第一位指示第一状态。第二锁存器耦合到第一阵列并且包括第二位，第二位指示第二状态。第一读取端口耦合到第一阵列，包括第一读取字线和第一读取位线。第一读取字线耦合到第一锁存器和第一列，并基于第一位置位第一可用信号。第一读取位线耦合到第一行并且基于第一可用信号和第一单元产生第一就绪信号。第二读取端口耦合到第一阵列并且包括第二读取字线和第二读取位线。第二读取字线耦合到第二锁存器和第一列，并基于第二位置位第二可用信号。第二读取位线耦合到第一行，并且基于第二读取字线和第一单元产生第二就绪信号。

18. 发明申请

US20100257339A1 Dependency Matrix with Improved Performance 审中-公开
标题翻译：具有改进性能的依赖矩阵
公开(公告)号：US20100257339A1
公开(公告)日：2010-10-07
申请号：US12417831
申请日：2009-04-03
申请人： Mary D. Brown , William E. Burky , Dung Q. Nguyen , Todd A. Venton
发明人： Mary D. Brown , William E. Burky , Dung Q. Nguyen , Todd A. Venton
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a processor execution queue and each cell in the first array represents a dependency relationship between two instructions in the processor execution queue. A clear port couples to the first array and clears a column of the first array. A producer status module couples to the clear port and the first array and determines an execution status of a producer instruction, wherein the producer instruction is an instruction in the processor execution queue. An available-status port couples to the first array and the producer status module and sets a read wordline column corresponding to the producer instruction based on the execution status of the producer instruction. The available-status port deasserts the read wordline column in response to a selection of the producer for execution. The available-status port reasserts the read wordline column in the event the producer status module determines the producer instruction has been rejected. The clear port clears the column of the first array corresponding to the producer instruction in the event the producer status module determines the producer instruction has been executed.
摘要翻译：具有依赖矩阵的处理器包括第一阵列，其包括以多个列排列的多个单元和多个行。每行代表处理器执行队列中的指令，第一个数组中的每个单元表示处理器执行队列中的两个指令之间的依赖关系。清除端口耦合到第一个数组，并清除第一个数组的列。生产者状态模块耦合到清除端口和第一阵列，并且确定生成器指令的执行状态，其中生成器指令是处理器执行队列中的指令。可用状态端口耦合到第一阵列和生成器状态模块，并且基于生成器指令的执行状态设置与生成器指令相对应的读字线列。可用状态端口取消对读取的字线列的响应，以选择要执行的生产者。在生产者状态模块确定生产者指令已被拒绝的情况下，可用状态端口重新发送读取字线列。在生产者状态模块确定生产者指令已执行的情况下，清除端口清除与生产者指令对应的第一个阵列的列。

19. 发明申请

US20100250902A1 Tracking Deallocated Load Instructions Using a Dependence Matrix 有权
标题翻译：使用依赖矩阵跟踪取消分配的加载指令
公开(公告)号：US20100250902A1
公开(公告)日：2010-09-30
申请号：US12410024
申请日：2009-03-24
申请人： Christopher M. Abernathy , Mary D. Brown , William E. Burky , Todd A. Venton
发明人： Christopher M. Abernathy , Mary D. Brown , William E. Burky , Todd A. Venton
IPC分类号： G06F9/312
CPC分类号： G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3857
摘要： A mechanism is provided for tracking deallocated load instructions. A processor detects whether a load instruction in a set of instructions in an issue queue has missed. Responsive to a miss of the load instruction, an instruction scheduler allocates the load instruction to a load miss queue and deallocates the load instruction from the issue queue. The instruction scheduler determines whether there is a dependence entry for the load instruction in an issue queue portion of a dependence matrix. Responsive to the existence of the dependence entry for the load instruction in the issue queue portion of the dependence matrix, the instruction scheduler reads data from the dependence entry of the issue queue portion of the dependence matrix that specifies a set of dependent instructions that are dependent on the load instruction and writes the data into a new entry in a load miss queue portion of the dependence matrix.
摘要翻译：提供了一种跟踪取消分配的加载指令的机制。处理器检测发送队列中的一组指令中的加载指令是否已经丢失。响应于加载指令的未命中，指令调度器将加载指令分配给加载未命中队列，并从发出队列中释放加载指令。指令调度器确定在依赖矩阵的发布队列部分中是否存在用于加载指令的依赖条目。响应于依赖矩阵的发布队列部分中的加载指令的依赖条目的存在，指令调度器从依赖矩阵的发布队列部分的依赖条目读取数据，该依赖矩阵指定一组依赖的依赖指令在加载指令中，将数据写入依赖矩阵的加载未命中队列部分中的新条目。

20. 发明授权

US07711929B2 Method and system for tracking instruction dependency in an out-of-order processor 失效
标题翻译：用于跟踪乱序处理器中的指令依赖性的方法和系统
公开(公告)号：US07711929B2
公开(公告)日：2010-05-04
申请号：US11847530
申请日：2007-08-30
申请人： William E. Burky , Krishnan Kailas
发明人： William E. Burky , Krishnan Kailas
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F9/3013 , G06F9/3838 , G06F9/3842 , G06F9/3855 , G06F9/3863
摘要： A method of tracking instruction dependency in a processor issuing instructions speculatively includes recording in an instruction dependency array (IDA) an entry for each instruction that indicates data dependencies, if any, upon other active instructions. An output vector read out from the IDA indicates data readiness based upon which instructions have previously been selected for issue. The output vector is used to select and read out issue-ready instructions from an instruction buffer.
摘要翻译：在处理器发布指令中跟踪指令依赖性的方法推测地包括在指令依赖性阵列（IDA）中记录指示其他活动指令的数据依赖性（如果有的话）的每个指令的条目。从IDA读出的输出向量基于先前已经选择了哪些指令进行发布来指示数据准备。输出向量用于从指令缓冲区中选择并读出准备就绪的指令。

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