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    • 15. 发明授权
    • Signal receiver with data precessing function
    • 具有数据进位功能的信号接收器
    • US07176721B2
    • 2007-02-13
    • US11022291
    • 2004-12-24
    • Andrew HoVladimir M. Stojanovic
    • Andrew HoVladimir M. Stojanovic
    • H03K17/16
    • H04L25/03057H04L25/028H04L25/0292H04L25/03343H04L25/061H04L25/4906
    • In a data-precessing receiver, a sampling circuit generates a plurality of samples of an incoming signal and stores the plurality of samples one after another in a first storage buffer. A first subset of the plurality of samples are transferred from the first storage buffer to a decoder circuit in response to each assertion of a first control signal, and a second subset of the plurality of samples are transferred from the first storage buffer to a tap weight update circuit in response to each assertion of a second control signal, the second strobe signal being asserted asynchronously with respect to the first control signal. The tap weight update circuit generates a plurality of updated tap weights based, at least in part, on the second subset of the plurality of samples.
    • 在数据进位接收机中,采样电路产生输入信号的多个采样,并将多个样本依次存储在第一存储缓冲器中。 响应于每个断言第一控制信号,多个样本的第一子集从第一存储缓冲器传送到解码器电路,并且多个样本的第二子集从第一存储缓冲器传送到抽头权重 响应于每个断言第二控制信号的更新电路,所述第二选通信号相对于所述第一控制信号被异步地断言。 抽头加权更新电路至少部分地基于多个样本的第二子集生成多个更新抽头加权。
    • 16. 发明申请
    • RAM-DAC for transmit preemphasis
    • RAM-DAC用于传输预加重
    • US20070025488A1
    • 2007-02-01
    • US11193916
    • 2005-07-29
    • Andrew HoFred ChenJared Zerbe
    • Andrew HoFred ChenJared Zerbe
    • H04L7/00
    • H04L25/03834H03H17/0294
    • Described are transmitters with RAM-DAC based pre-emphasis filters that can be updated adaptively without interfering with data transmission. The memory within the RAM-DAC is divided into active and inactive memory locations, in which active memory locations are those to be accessed in the near future, and consequently cannot be updated (written to) at a given time due without inducing a read/write conflict. One embodiment monitors incoming memory addresses to find an adequate time window for a write to take place without a read interference. Another embodiment includes two memory blocks with similar address space, one of which may be updated as the other is used to for data transmission. Some embodiments employ a RAM-DAC with reduced memory size and complexity.
    • 描述的是具有基于RAM-DAC的预加重滤波器的发射器,其可以自适应地更新而不干扰数据传输。 RAM-DAC内的存储器被分为有源和非活动存储器位置,其中有效存储器位置是在不久的将来被访问的存储器位置,因此不能在给定时间更新(写入),而不会引起读/ 写冲突。 一个实施例监视进入的存储器地址以找到足够的时间窗口,以便在没有读取干扰的情况下进行写入。 另一个实施例包括具有类似地址空间的两个存储器块,其中之一可以被更新,而另一个用于数据传输。 一些实施例采用具有减小的存储器大小和复杂性的RAM-DAC。
    • 20. 发明授权
    • Noise-tolerant signaling schemes supporting simplified timing and data recovery
    • 支持简化时序和数据恢复的耐噪声信令方案
    • US07672380B2
    • 2010-03-02
    • US11895415
    • 2007-08-23
    • Andrew HoVladimir StojanovicFred F. ChenElad AlonMark A. Horowitz
    • Andrew HoVladimir StojanovicFred F. ChenElad AlonMark A. Horowitz
    • H04B3/00H04B1/10H03D1/04H04L5/16
    • H04L47/10H04L5/20H04L25/0276
    • Described are communication systems that convey differential and common-mode signals over the same differential channel. Noise-tolerant communication schemes use low-amplitude common-mode signals that are easily rejected by differential receivers, thus allowing for very high differential data rates. Some embodiments employ the common-mode signals to transmit backchannel signals for adjusting the characteristics of the differential transmitter. Backchannel control signals are effectively conveyed even if the forward channel transmitter is so maladjusted that the received differential data is unrecognizable. Systems in accordance with the above-described embodiments obtain these advantages without additional pins or communications channels, and are compatible with both AC-coupled and DC-coupled communications channels. Data coding schemes and corresponding data recovery circuits eliminate the need for complex, high-speed CDR circuits.
    • 描述了通过相同的差分通道传送差分和共模信号的通信系统。 耐噪声通信方案使用容易被差分接收机拒绝的低振幅共模信号,从而允许非常高的差分数据速率。 一些实施例采用共模信号来发送用于调整差分发射机的特性的反向信道信号。 即使前向信道发射机被调整不正确,接收到的差分数据是无法识别的,反向信道控制信号也被有效地传送。 根据上述实施例的系统在没有附加引脚或通信信道的情况下获得这些优点,并且与AC耦合和DC耦合通信信道兼容。 数据编码方案和相应的数据恢复电路不需要复杂的高速CDR电路。