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11. 发明授权

US06765273B1 Device structure and method for reducing silicide encroachment 失效
公开(公告)号：US06765273B1
公开(公告)日：2004-07-20
申请号：US09115405
申请日：1998-07-14
申请人： Robert S. Chau , Ebrahim Andideh , Mitch C. Taylor , Chia-Hong Jan , Julie Tsai
发明人： Robert S. Chau , Ebrahim Andideh , Mitch C. Taylor , Chia-Hong Jan , Julie Tsai
IPC分类号： H01L2976
CPC分类号： H01L29/66515 , H01L21/28525 , H01L21/28562 , H01L21/823814 , H01L21/823835 , H01L21/823878 , H01L29/41766 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/66636
摘要： A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. A sidewall spacer which is formed adjacent to the electrode has a height which is greater than the sum of the thickness of the electrode and the thickness of the silicide layer.

12. 发明授权

US06518155B1 Device structure and method for reducing silicide encroachment 失效
公开(公告)号：US06518155B1
公开(公告)日：2003-02-11
申请号：US08884912
申请日：1997-06-30
申请人： Robert S. Chau , Ebrahim Andideh , Mitch C. Taylor , Chia-Hong Jan , Julie Tsai
发明人： Robert S. Chau , Ebrahim Andideh , Mitch C. Taylor , Chia-Hong Jan , Julie Tsai
IPC分类号： H01L213205
CPC分类号： H01L29/66515 , H01L21/28525 , H01L21/28562 , H01L21/823814 , H01L21/823835 , H01L21/823878 , H01L29/41766 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/66636
摘要： A semiconductor device having a novel spacer structure and method of fabrication. The present invention describes a semiconductor device which has an electrode with a first thickness. A silicide layer having a second thickness is formed on the electrode. A sidewall spacer which is formed adjacent to the electrode has a height which is greater than the sum of the thickness of the electrode and the thickness of the silicide layer.

13. 发明授权

US06198142B1 Transistor with minimal junction capacitance and method of fabrication 失效
标题翻译：具有最小结电容的晶体管和制造方法
公开(公告)号：US06198142B1
公开(公告)日：2001-03-06
申请号：US09127349
申请日：1998-07-31
申请人： Robert S. Chau , Chia-Hong Jan , Paul Packan , Mitchell C. Taylor
发明人： Robert S. Chau , Chia-Hong Jan , Paul Packan , Mitchell C. Taylor
IPC分类号： H01L2976
CPC分类号： H01L29/66636 , H01L21/26533 , H01L29/0653 , H01L29/165 , H01L29/665 , H01L29/66537 , H01L29/7834
摘要： A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.
摘要翻译：在该制造方法中具有最小结电容的新型MOS晶体管。根据本发明，在半导体衬底的第一表面上形成栅介质层。然后在栅极电介质层上形成栅电极。接下来，在栅电极的相对侧上的半导体衬底中形成一对凹部。然后在每个凹部的表面上形成介电层。然后将半导体材料沉积到凹槽中以形成一对源极/漏极区域。

14. 发明授权

US5908313A Method of forming a transistor 失效
标题翻译：形成晶体管的方法
公开(公告)号：US5908313A
公开(公告)日：1999-06-01
申请号：US775410
申请日：1996-12-31
申请人： Robert S. Chau , Chia-Hong Jan , Paul Packan , Mitchell C. Taylor
发明人： Robert S. Chau , Chia-Hong Jan , Paul Packan , Mitchell C. Taylor
IPC分类号： H01L21/225 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/417 , H01L29/49
CPC分类号： H01L29/66477 , H01L21/26586 , H01L21/28052 , H01L29/0653 , H01L29/1083 , H01L29/41766 , H01L29/41783 , H01L29/4925 , H01L29/66628 , H01L29/66636 , H01L21/2254 , H01L21/2257 , H01L21/26506
摘要： A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.
摘要翻译：在该制造方法中具有最小结电容的新型MOS晶体管。根据本发明，在半导体衬底的第一表面上形成栅介质层。然后在栅极电介质层上形成栅电极。接下来，在栅电极的相对侧上的半导体衬底中形成一对凹部。然后在每个凹部的表面上形成介电层。然后将半导体材料沉积到凹槽中以形成一对源极/漏极区域。

15. 发明授权

US07338873B2 Method of fabricating a field effect transistor structure with abrupt source/drain junctions 有权
公开(公告)号：US07338873B2
公开(公告)日：2008-03-04
申请号：US11437569
申请日：2006-05-19
申请人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
发明人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/0262 , H01L21/2022 , H01L29/0646 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/41766 , H01L29/41783 , H01L29/4925 , H01L29/66477 , H01L29/66492 , H01L29/665 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

16. 发明授权

US6121100A Method of fabricating a MOS transistor with a raised source/drain extension 失效
标题翻译：制造具有升高的源极/漏极延伸的MOS晶体管的方法
公开(公告)号：US6121100A
公开(公告)日：2000-09-19
申请号：US1337
申请日：1997-12-31
申请人： Ebrahim Andideh , Lawrence Brigham , Robert S. Chau , Tahir Ghani , Chia-Hong Jan , Justin Sandford , Mitchell C. Taylor
发明人： Ebrahim Andideh , Lawrence Brigham , Robert S. Chau , Tahir Ghani , Chia-Hong Jan , Justin Sandford , Mitchell C. Taylor
IPC分类号： H01L21/225 , H01L21/336 , H01L21/8238 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/2254 , H01L21/823814 , H01L29/41766 , H01L29/41783 , H01L29/456 , H01L29/4925 , H01L29/66636 , H01L29/7834 , H01L29/665 , H01L29/66545
摘要： A method of forming a MOS transistor. According to the method of the present invention, a pair of source/drain contact regions are formed on opposite sides of a gate electrode. After forming the pair of source/drain contact regions, semiconductor material is deposited onto opposite sides of the gate electrode. Dopants are then diffused from the semiconductor material into the substrate beneath the gate electrode to form a pair of source/drain extensions.
摘要翻译：一种形成MOS晶体管的方法。根据本发明的方法，在栅电极的相对侧上形成一对源极/漏极接触区域。在形成一对源极/漏极接触区域之后，半导体材料沉积在栅电极的相对侧上。掺杂剂然后从半导体材料扩散到栅电极下方的衬底中，以形成一对源/漏扩展。

17. 发明授权

US09640634B2 Field effect transistor structure with abrupt source/drain junctions 有权
公开(公告)号：US09640634B2
公开(公告)日：2017-05-02
申请号：US12700637
申请日：2010-02-04
申请人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
发明人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
IPC分类号： H01L21/336 , H01L29/66 , H01L29/08 , H01L29/10 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/417 , H01L29/49 , H01L29/78 , H01L21/20
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/0262 , H01L21/2022 , H01L29/0646 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/41766 , H01L29/41783 , H01L29/4925 , H01L29/66477 , H01L29/66492 , H01L29/665 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

18. 发明授权

US09570467B2 High voltage three-dimensional devices having dielectric liners 有权
标题翻译：具有电介质衬垫的高压三维器件
公开(公告)号：US09570467B2
公开(公告)日：2017-02-14
申请号：US14641117
申请日：2015-03-06
申请人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
发明人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC分类号： H01L21/84 , H01L27/12 , H01L29/66 , H01L21/8234 , H01L21/02 , H01L21/28 , H01L29/423 , H01L29/51
CPC分类号： H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.
摘要翻译：描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。第一栅极结构包括第一栅极电介质，第一栅极电极和第一间隔物。第一栅极电介质由设置在第一鳍状物活性区域上并沿着第一间隔物的侧壁的第一介电层和设置在第一介电层上并沿着第一间隔物的侧壁的第二不同介电层组成。半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。第二栅极结构包括第二栅极电介质，第二栅电极和第二间隔物。第二栅极电介质由设置在第二鳍状物活性区域和第二间隔物的侧壁上的第二介电层构成。

19. 发明申请

US20170005187A1 FIN-BASED SEMICONDUCTOR DEVICES AND METHODS 审中-公开
标题翻译：基于FIN的半导体器件和方法
公开(公告)号：US20170005187A1
公开(公告)日：2017-01-05
申请号：US15100286
申请日：2014-01-24
申请人： Walid M. Hafez , Chia-Hong Jan
发明人： Walid M. Hafez , Chia-Hong Jan
IPC分类号： H01L29/74 , H01L29/66 , H01L29/417 , H01L27/02 , H01L29/06
CPC分类号： H01L29/74 , H01L21/2255 , H01L27/0262 , H01L29/0649 , H01L29/41716 , H01L29/66363 , H01L29/785
摘要： Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.
摘要翻译：公开了半导体器件，集成电路器件和方法的实施例。在一些实施例中，半导体器件可以包括设置在衬底上的第一鳍和第二鳍。第一翅片可以具有包括设置在第二材料和基底之间的第一材料的部分，第二材料设置在第三材料和第一材料之间，第三材料设置在第四材料和第二材料之间。第一和第三材料可以由第一类型的非本征半导体形成，并且第二和第四材料可以由第二种不同类型的外在半导体形成。第二翅片可以与第一翅片横向分离并且与第一，第二，第三或第四材料中的至少一个物质连接。可以公开和/或要求保护其他实施例。

20. 发明申请

US20150187709A1 METAL FUSE BY TOPOLOGY 有权
标题翻译：金属保险丝通过拓扑学
公开(公告)号：US20150187709A1
公开(公告)日：2015-07-02
申请号：US14142629
申请日：2013-12-27
申请人： Chen-Guan Lee , Walid M. Hafez , Chia-Hong Jan
发明人： Chen-Guan Lee , Walid M. Hafez , Chia-Hong Jan
IPC分类号： H01L23/62 , H01L21/3205 , H01L21/02
CPC分类号： H01L23/62 , H01L21/0217 , H01L21/32055 , H01L23/5256 , H01L2224/16225 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： Embodiments of the present disclosure describe techniques and configurations for overcurrent fuses in integrated circuit (IC) devices. In one embodiment, a device layer of a die may include a first line structure with a recessed portion between opposite end portions and two second line structures positioned on opposite sides of the first line structure. An isolation material may be disposed in the gaps between the line structures and in a first recess defined by the recessed portion. The isolation material may have a recessed portion that defines a second recess in the first recess, and a fuse structure may be disposed in the second recess. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于集成电路（IC）装置中的过电流保险丝的技术和配置。在一个实施例中，管芯的器件层可以包括在相对端部之间具有凹陷部分的第一线结构和位于第一线结构的相对侧上的两个第二线结构。隔离材料可以设置在线结构之间的间隙中，并且可以设置在由凹部限定的第一凹部中。隔离材料可以具有限定第一凹部中的第二凹部的凹部，并且熔丝结构可以设置在第二凹部中。可以描述和/或要求保护其他实施例。

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