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11. 发明申请

US20090265534A1 Fairness, Performance, and Livelock Assessment Using a Loop Manager With Comparative Parallel Looping 审中-公开
标题翻译：使用循环管理器进行比较并行循环的公平性，性能和动态锁定评估
公开(公告)号：US20090265534A1
公开(公告)日：2009-10-22
申请号：US12104638
申请日：2008-04-17
申请人： Duane A. Averill , Anthony D. Drumm , Christopher T. Phan , Brian T. Vanderpool , Sharon D. Vincent
发明人： Duane A. Averill , Anthony D. Drumm , Christopher T. Phan , Brian T. Vanderpool , Sharon D. Vincent
IPC分类号： G06F9/30
CPC分类号： G06F9/4881
摘要： A method, apparatus, and computer program are provided for assessing fairness, performance, and livelock in a logic development process utilizing comparative parallel looping. Multiple loop macros are generated, the multiple loop macros respectively correspond to multiple processor threads, and the multiple loop macros are parallel comparative loop macros. The multiple processor threads for the multiple loop macros are executed in which a common resource is accessed. A forward performance of each of the multiple processor threads is verified. The forward performance of the multiple processor threads is compared with each other. It is determined whether any of the multiple processor threads fails to meet a minimum loop count or a minimum loop time. It is determined whether any of the multiple processor threads exceeds a maximum loop count or a maximum loop time. It is recognized whether fairness is maintained during the execution of the multiple processor threads.
摘要翻译：提供了一种方法，装置和计算机程序，用于评估利用比较并行循环的逻辑开发过程中的公平性，性能和活动锁定。生成多个循环宏，多个循环宏分别对应多个处理器线程，多个循环宏是并行的比较循环宏。执行多循环宏的多个处理器线程，其中访问公共资源。验证多个处理器线程中的每一个的前向性能。将多个处理器线程的前向性能相互比较。确定多个处理器线程中的任何一个线程是否不能满足最小循环计数或最小循环时间。确定多个处理器线程中的任何一个线程是否超过最大循环计数或最大循环时间。公认在执行多个处理器线程期间是否保持公平性。

12. 发明授权

US5436849A Incremental logic synthesis system for efficient revision of logic circuit designs 失效
标题翻译：增量逻辑综合系统，用于逻辑电路设计的有效修改
公开(公告)号：US5436849A
公开(公告)日：1995-07-25
申请号：US15567
申请日：1993-02-09
申请人： Anthony D. Drumm
发明人： Anthony D. Drumm
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： An apparatus and method for incremental logic synthesis that transforms a revised technology-independent electronic digital circuit design into a revised technology-dependent design deviating as little as possible from the original technology-dependent design. The incremental synthesis procedure includes a forward sweep technique where nodes in the revised technology-independent model and the original technology-dependent design are compared to see if they map the same logical function of the inputs common to both designs. A backward sweep technique compares nodes in the revised technology-independent model to the unrevised technology-dependent design to see which outputs common to both map the same logical node functions. Portions of the revised technology-independent model with the same logical function as corresponding parts of the unchanged technology-dependent design are progressively eliminated, reducing the revised technology-independent design to an "increment" that is then conventionally synthesized and merged with the unchanged technology-dependent design to yield the revised technology-dependent design having only the minimal necessary revisions.
摘要翻译：用于增量逻辑综合的装置和方法，其将经修订的与技术无关的电子数字电路设计转换为与原始技术相关的设计尽可能偏离的经修订的技术相关设计。增量合成过程包括前向扫描技术，其中将经修订的与技术无关的模型中的节点与原始技术相关的设计进行比较，以查看它们是否映射两个设计共同的输入的相同逻辑功能。反向扫描技术将经修订的与技术无关的模型中的节点与未修改的技术相关设计进行比较，以查看哪些输出共同映射相同的逻辑节点功能。与技术相关设计不变的相应部分具有相同逻辑功能的修订的与技术无关的模型的部分逐渐消除，将修订的与技术无关的设计减少到“增量”，然后通过常规合成并与未更改的技术依赖设计来产生修改后的技术依赖设计，只有极少的必要修订。

13. 发明授权

US5003487A Method and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesis 失效
标题翻译：用于在逻辑合成期间对与技术无关的逻辑模型执行定时校正变换的方法和装置
公开(公告)号：US5003487A
公开(公告)日：1991-03-26
申请号：US212529
申请日：1988-06-28
申请人： Anthony D. Drumm , Randall C. Itskin , Kenneth W. Todd
发明人： Anthony D. Drumm , Randall C. Itskin , Kenneth W. Todd
IPC分类号： H03K19/00 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/505
摘要： A computer program is disclosed providing a sequence of automated logic synthesis routines having three phases. Phase I identifies an estimated critical path by assuming optimum allocation within a "best-fit" preliminary assignment of the technology to a technology-independent model, and optimizes the estimated model for speed. Phase II provides a technology-legal model, and ends by calculating the actual timing provided by the technology-legal model. Phase III uses self-limiting routines, and routines that are unlikely to produce technology violations, to fine tune the production and performance characteristics of the legal model.

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