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11. 发明授权

US5619066A Memory for an electronic token 失效
标题翻译：内存为电子令牌
公开(公告)号：US5619066A
公开(公告)日：1997-04-08
申请号：US299040
申请日：1994-08-31
申请人： Stephen M. Curry , Michael L. Bolan , Kevin E. Deierling , William L. Payne, II , Hal Kurkowski , Donald R. Dias , Gary V. Zanders , Robert D. Lee , Guenther H. Lehmann
发明人： Stephen M. Curry , Michael L. Bolan , Kevin E. Deierling , William L. Payne, II , Hal Kurkowski , Donald R. Dias , Gary V. Zanders , Robert D. Lee , Guenther H. Lehmann
IPC分类号： G01K1/02 , G01K3/10 , G01K7/24 , G06F1/00 , G06F1/20 , G06F3/023 , G06F3/038 , G06K7/00 , G06K19/07 , G11C5/00 , G11C5/06 , G11C7/06 , G11C7/24 , G11C8/20 , H01L23/58 , G06K19/06
CPC分类号： H01L23/58 , G01K1/028 , G01K3/10 , G01K7/245 , G06F1/206 , G06F21/73 , G06F21/79 , G06F3/0383 , G06F3/04897 , G06K19/07 , G06K7/0021 , G11C5/066 , G11C5/143 , G11C7/065 , G11C7/24 , G11C8/20 , H01L2924/0002 , H01L2924/3011 , Y02B60/1275
摘要： A serial-port memory is positioned in a substantially token-shaped body. The substantially token-shaped body has a perimeter and a flange extending from a portion of the perimeter. The serial-port memory comprises a serial port, a scratchpad memory coupled to the serial port, a second memory coupled to the scratchpad memory; and control logic coupled to the serial port and the scratchpad and second memories. The control logic transfers information from the scratchpad memory to the second memory as a block pursuant to a block transfer command received at the serial port. The electronic token has a first electrically conductive surface and a second electrically conductive surface that combines to create a hollow cavity and the serial port, scratchpad memory, second memory, and control logic positioned inside the hollow cavity, the first conductive surface and the second conductive surface can be electrically coupled to transmit electrical signals generated by the serial port, scratchpad memory, second memory, and control logic and to receive externally generated electrical signals. The first electrically conductive surface and the second electrically conductive surface are preferably planar. The control logic includes a cyclic redundancy check generator. Third and fourth memories can be coupled to the scratchpad memory, wherein the control logic transfers information as a block from the scratchpad memory to one of the second, third, and fourth memories pursuant to a block transfer command received at the serial port.
摘要翻译：串行端口存储器位于基本上令牌形的主体中。基本上令牌形的主体具有从周边的一部分延伸的周边和凸缘。串行端口存储器包括串行端口，耦合到串行端口的暂存器存储器，耦合到暂存器存储器的第二存储器; 以及耦合到串行端口和暂存器和第二存储器的控制逻辑。控制逻辑根据在串行端口处接收到的块传送命令，将信息从暂存器存储器传送到第二存储器作为块。电子令牌具有第一导电表面和第二导电表面，其组合以产生中空空腔，以及定位在空腔内部的串行端口，暂存器存储器，第二存储器和控制逻辑，第一导电表面和第二导电表面可以电耦合以传输由串行端口，暂存器存储器，第二存储器和控制逻辑产生的电信号，并且接收外部产生的电信号。第一导电表面和第二导电表面优选是平面的。控制逻辑包括循环冗余校验生成器。第三和第四存储器可以耦合到暂存器存储器，其中控制逻辑根据在串行端口接收的块传送命令，将作为块的信息从暂存器存储器传送到第二，第三和第四存储器之一。

12. 发明授权

US4943804A Electronic key locking circuitry 失效
标题翻译：电子钥匙锁定电路
公开(公告)号：US4943804A
公开(公告)日：1990-07-24
申请号：US412767
申请日：1989-09-26
申请人： Robert D. Lee , Donald R. Dias
发明人： Robert D. Lee , Donald R. Dias
IPC分类号： G07C9/00 , G11C7/24
CPC分类号： G11C7/24 , G07C9/00857
摘要： An electronic key which responds to different sets of valid commands over its lifetime, depending on the state of certain circuits within the electronic key.(1) After initial fabrication of the electronic key, the electronic key recognizes a first set of valid commands and ignores all other commands.(2) After the electronic key is tested and a countdown circuit within the electronic key has been calibrated, a fusing element inside the electronic key is blown. This reduces the number of valid commands recognizable by the electronic key. Thus, the key is now restricted to a second set of valid commands.(3) The electronic key is then shipped to an OEM, who programs data into the key and also programs the length of time of the countdown timer. The OEM then sets an R-S flip-flop in the electronic key, which causes certain of the second set of commands to be ignored. Thus, the key will now respond only to a third set of valid commands.(4) The electronic key is then shipped to an end user. The first valid command recognized by the electronic key, after the R-S flip-flop has been set, starts the countdown timer.(5) After the countdown timer has timed out, the number of valid commands is further reduced. Thus, the key will now respond only to a fourth (very small) set of valid commands.
摘要翻译：一种电子钥匙，它根据电子钥匙内某些电路的状态，在其使用寿命期间响应不同的有效命令集。（1）电子钥匙的初始制造后，电子钥匙识别第一组有效命令，并忽略所有其他命令。（2）在电子钥匙被测试并且电子钥匙内的倒计时电路已被校准之后，电子钥匙内的定影元件被吹动。这减少了电子钥匙可识别的有效命令的数量。因此，密钥现在被限制到第二组有效命令。（3）电子钥匙然后发运给OEM，他们将数据编入密钥，并对倒数计时器的时间长度进行编程。然后，OEM在电子钥匙中设置一个R-S触发器，这导致第二组命令中的某些被忽略。因此，密钥现在将仅响应第三组有效命令。（4）电子钥匙然后运送到最终用户。在电子钥匙识别的第一个有效指令，在R-S触发器置1之后，启动倒数计时器。（5）倒数计时器超时后，进一步减少有效命令的数量。因此，密钥现在将仅响应第四（非常小）的有效命令集。

13. 发明授权

US4897860A Programmable time base circuit with protected internal calibration 失效
标题翻译：可编程时基电路，具有受保护的内部校准
公开(公告)号：US4897860A
公开(公告)日：1990-01-30
申请号：US163279
申请日：1988-03-02
申请人： Robert D. Lee , Donald R. Dias
发明人： Robert D. Lee , Donald R. Dias
IPC分类号： G04F1/00 , G04G3/02 , G11C7/24
CPC分类号： G11C7/24 , G04F1/005 , G04G3/02
摘要： A timeout circuit with internal calibration includes an oscillator (11) for generating an initial frequency for division by a modulo-n counter (20). The counter (20) receives the value of n from a calibration register (22) and divides the frequency of the oscillator by the value of n. A gate (26) prevents alteration of the contents of the register (22). The output of the counter (20) provides a calibrated frequency which is further divided by a day counter (32) for output to a countdown counter (34). The countdown counter (34) provides a predetermined countdown of the signal output by the day counter (32) and, at the end of the count, generates a Timeout signal. The predetermined countdown value is determined by a value stored in a register (36) which can be protected by a customer lock out circuit (42).
摘要翻译：具有内部校准的超时电路包括用于产生用于由模n计数器（20）划分的初始频率的振荡器（11）。计数器（20）从校准寄存器（22）接收n的值，并将振荡器的频率除以n的值。门（26）防止寄存器（22）的内容的改变。计数器（20）的输出提供校准频率，进一步由日间计数器（32）除以输出到倒数计数器（34）。倒计时计数器（34）提供由日间计数器（32）输出的信号的预定倒计时，并且在计数结束时产生超时信号。预定的倒计时值由存储在可由客户锁定电路（42）保护的寄存器（36）中的值确定。

14. 发明授权

US4870401A Electronic key locking circuitry 失效
标题翻译：电子钥匙锁定电路
公开(公告)号：US4870401A
公开(公告)日：1989-09-26
申请号：US163281
申请日：1988-03-02
申请人： Robert D. Lee , Donald R. Dias
发明人： Robert D. Lee , Donald R. Dias
IPC分类号： G07C9/00 , G11C7/24
CPC分类号： G11C7/24 , G07C9/00857
摘要： An electronic key which responds to different sets of valid commands over its lifetime, depending on the state of certain circuits within the electronic key,(1) After initial fabrication of the electronic key, the electronic key recognizes a first set of valid commands and ignores all other commands,(2) After the electronic key is tested and a countdown circuit within the electronic key has been calibrated, a fusing element inside the electronic key is blown. This reduces the number of valid commands recognizable by the electronic key. Thus, the key is now restricted to a second set of valid commands,(3) The electronic key is then shipped to an OEM, who programs data into the key and also programs the length of time of the countdown timer. The OEM then sets an R-S flip-flop in the electronic key, which causes certain of the second set of commands to be ignored. Thus, the key will now respond only to a third set of valid commands,(4) The electronic key is then shipped to an end user. The first valid command recognized by the electronic key, after the R-S flip-flop has been set, starts the countdown timer,(5) After the countdown timer has timed out, the number of valid commands is further reduced. Thus, the key will now respond only to a fourth (very small) set of valid commands.
摘要翻译：根据电子钥匙内某些电路的状态，电子钥匙在其寿命期内对不同的有效命令集进行响应，（1）电子钥匙在初始制作之后，识别第一组有效命令并忽略所有其他命令，（2）在电子钥匙被测试并且电子钥匙中的倒计时电路已被校准之后，电子钥匙内部的定影元件被熔断。这减少了电子钥匙可识别的有效命令的数量。因此，现在的密钥现在仅限于第二组有效的命令，（3）电子钥匙然后运送到OEM，他们将数据编入密钥，并对倒数计时器的时间长度进行编程。然后，OEM在电子钥匙中设置一个R-S触发器，这导致第二组命令中的某些被忽略。因此，密钥现在将仅响应第三组有效命令，（4）电子钥匙然后发送给最终用户。电子钥匙识别的第一个有效指令，在R-S触发器置1之后，启动倒数计时器，（5）倒数计时器超时后，有效命令数进一步减少。因此，密钥现在将仅响应第四（非常小）的有效命令集。

15. 发明授权

US5867006A Battery charger 失效
公开(公告)号：US5867006A
公开(公告)日：1999-02-02
申请号：US901068
申请日：1997-07-28
申请人： Donald R. Dias , Robert D. Lee
发明人： Donald R. Dias , Robert D. Lee
IPC分类号： G01K1/00 , G01K5/24 , G01R31/36 , G06F15/00 , G06F19/00 , H01M10/42 , H01M10/44 , H01M10/46 , H01M10/48 , H02J7/00
CPC分类号： G01K7/13 , H01M10/425 , H01M10/4257 , H01M10/48 , H02J7/0004
摘要： A battery charger with charging parameter values derived from communication with a battery pack to be charged. Communication is over a one-wire bus with battery pack transmissions in response to charger inquiries. The battery charger may be in the form an integrated circuit driving a power transistor or other controllable DC supply. A battery pack may contain a program with multiple charging currents and charging interval termination methods such as time, temperature rise, and incremental voltage polarity. A lack of communication may be invoke a default charging program or denial of access to the charger. The charger also communicates over a high-speed three-wire bus with an external computer for analysis of identification information acquired from the battery and for control of the charger.

16. 发明授权

US5694024A Battery charger 失效
公开(公告)号：US5694024A
公开(公告)日：1997-12-02
申请号：US764285
申请日：1996-12-12
申请人： Donald R. Dias , Robert D. Lee
发明人： Donald R. Dias , Robert D. Lee
IPC分类号： G01K1/00 , G01K5/24 , G01R31/36 , G06F15/00 , G06F19/00 , H01M10/42 , H01M10/44 , H01M10/46 , H01M10/48 , H02J7/00
CPC分类号： G01K7/13 , H01M10/425 , H01M10/4257 , H01M10/48 , H02J7/0004
摘要： A battery charger with charging parameter values derived from communication with a battery pack to be charged. Communication is over a one-wire bus with battery pack transmissions in response to charger inquiries. The battery charger may be in the form an integrated circuit driving a power transistor or other controllable DC supply. A battery pack may contain a program with multiple charging currents and charging interval termination methods such as time, temperature rise, and incremental voltage polarity. A lack of communication may be invoke a default charging program or denial of access to the charger. The charger also communicates over a high-speed three-wire bus with an external computer for analysis of identification information acquired from the battery and for control of the charger.

17. 发明授权

US4984291A Coded communication system with shared symbols 失效
标题翻译：具有共享符号的编码通信系统
公开(公告)号：US4984291A
公开(公告)日：1991-01-08
申请号：US282008
申请日：1988-12-09
申请人： Donald R. Dias , Robert D. Lee
发明人： Donald R. Dias , Robert D. Lee
IPC分类号： H04B1/16
CPC分类号： H04W52/0229
摘要： A data communication system, including at least one base station and at least one portable module 120, wherein the portable module 120 transmits data on a high frequency, and the base station transmits data on a much lower frequency. Transmissions by the base station use a pulse-width modulation scheme where the most commonly used signals correspond to the shortest pulse. A "read" command is encoded as the same pulse width as one of the two write commands. Since the direction of data transmission is known in overhead, there will be no ambiguity.
摘要翻译：一种包括至少一个基站和至少一个便携式模块120的数据通信系统，其中便携式模块120以高频率发送数据，并且基站以低得多的频率发送数据。基站的传输使用脉冲宽度调制方案，其中最常用的信号对应于最短脉冲。 “读”命令被编码为与两个写命令之一相同的脉冲宽度。由于数据传输的方向在开销上是已知的，所以不会有歧义。

18. 发明授权

US4730121A Power controller for circuits with battery backup 失效
标题翻译：电池备用电路的电源控制器
公开(公告)号：US4730121A
公开(公告)日：1988-03-08
申请号：US24687
申请日：1987-03-11
申请人： Robert D. Lee , Donald R. Dias
发明人： Robert D. Lee , Donald R. Dias
IPC分类号： H02J9/06 , H02J9/02
CPC分类号： H02J9/061 , Y10T307/615 , Y10T307/625 , Y10T307/735
摘要： A power controller for selectively coupling the voltage from a primary power source to a power output terminal or coupling the voltage from a battery backup input terminal to the power output terminal includes circuitry for receiving a reset or isolation signal. After receipt of the isolation signal when the primary power source is above a first threshold voltage, the primary power source and the backup battery source will be isolated from the output power terminal on the next occurrence of the removal of the voltage from the primary power source.
摘要翻译：用于选择性地将来自主电源的电压耦合到电力输出端子或将来自电池备用输入端子的电压耦合到电力输出端子的功率控制器包括用于接收复位或隔离信号的电路。当主电源高于第一阈值电压时，在接收到隔离信号之后，主电源和备用电池源将在下一次从主电源去除电压时与输出电源端子隔离。

19. 发明授权

US4948954A Interface for receiving electronic tokens 失效
标题翻译：接收电子令牌的接口
公开(公告)号：US4948954A
公开(公告)日：1990-08-14
申请号：US352596
申请日：1989-05-15
申请人： Donald R. Dias
发明人： Donald R. Dias
IPC分类号： G06F3/023 , G06F3/038 , G06K7/00 , G06K19/077 , G11C5/00 , G11C5/06 , G11C7/24 , G11C8/20 , H04B1/40
CPC分类号： G11C8/20 , G06F3/0383 , G06F3/04897 , G06K19/047 , G06K19/0706 , G06K19/07743 , G06K7/0021 , G06K7/0086 , G11C5/00 , G11C5/066 , G11C7/24 , H04B1/403
摘要： A physical interface configuration which provides rapid contact to a two-terminal coin-shaped electronic token data module. A slot, dimensioned to receive electronic tokens, includes a grounded contact positioned to make contact to the edge of a token which may be inserted, and two data contacts which are positioned to make contact to the opposite faces of the token. Each of the data contacts is connected to an open-collector interface circuit, including a pull-up resistor which will bring the potential of the contact high when the slot is empty. The token is shaped so that its edge, and one of its faces, are connected to the token's ground line, and the other face is the token's data line. Thus, when a token is inserted (no matter which way the token is facing), one of the two data contacts will be immediately pulled to ground, by short-circuiting across the ground plane of the token. The system can thereby recognize that a token has been inserted, and that the other data contact (the one which was not shorted to ground) can communicate with the token's data line. Thus, even though the token itself is asymmetric, and even though the directional orientation of the token is not initially known to the system, no physical asymmetry needs to be introduced into the token or the slot to assure proper data interface.
摘要翻译：物理接口配置，其提供与两端硬币形电子令牌数据模块的快速接触。尺寸设计为接收电子标记的插槽包括定位成与可插入的令牌的边缘接触的接地触点，以及定位成与令牌的相对面接触的两个数据触点。每个数据触点连接到集电极开路接口电路，包括一个上拉电阻，当插槽为空时，该电阻将使触点的电位变高。令牌的形状使得其边缘和其一个面部连接到令牌的接地线，另一个面是令牌的数据线。因此，当插入令牌（无论令牌所面对的方式）时，两个数据触点中的一个将通过跨越令牌的接地平面的短路被立即拉到地。因此，系统可以识别出已经插入了令牌，并且其他数据联系人（未被接地的短路接口）可以与令牌的数据线通信。因此，即使令牌本身是不对称的，并且即使令牌的方向定向不是系统最初已知的，所以不需要将物理不对称性引入到令牌或时隙中以确保正确的数据接口。

20. 发明授权

US4510584A MOS Random access memory cell with nonvolatile storage 失效
标题翻译： MOS随机存取存储单元，具有非易失性存储
公开(公告)号：US4510584A
公开(公告)日：1985-04-09
申请号：US454418
申请日：1982-12-29
申请人： Donald R. Dias , Daniel C. Guterman , Robert J. Proebsting , Horst Leuschner
发明人： Donald R. Dias , Daniel C. Guterman , Robert J. Proebsting , Horst Leuschner
IPC分类号： G11C14/00 , G11C11/40
CPC分类号： G11C14/00
摘要： A nonvolatile random access memory cell (10) includes a static random access memory circuit and a corresponding nonvolatile memory circuit. The volatile memory circuit operates in a conventional manner and has first and second data states. Upon receipt of a store command signal a charge storage node is driven to either a first or a second charge state, depending upon the data state in the volatile memory circuit. For one charge state the charge storage signal is gated through a transistor (64) and a capacitor (68) to a floating gate node (44). Charge is transferred to and from the floating gate node (44) through current tunneling elements (48,50) which comprise a dielectric fabricated on a monocrystalline substrate. For the recall operation a recall command signal is applied to a transistor (52) which couples a transistor (42) to the DATA node (22) of the volatile memory circuit. If a positive charge state has been stored at the charge storage node (44) the transistor (42) is rendered conductive to pull the DATA node (22) to ground to restore the data state to the volatile memory circuit. If a negative charge state has been stored at the charge storage node (44) there is no load applied to either the DATA node (20) or the DATA node (22). The cross-couple transistors, (12,14) are fabricated to have different lengths such that the node (22) is driven to a high voltage state whenever a default condition is encountered, thereby restoring the original data state to the volatile memory circuit.
摘要翻译：非易失性随机存取存储器单元（10）包括静态随机存取存储器电路和相应的非易失性存储器电路。易失性存储器电路以常规方式工作并具有第一和第二数据状态。在接收到存储命令信号时，根据易失性存储器电路中的数据状态，电荷存储节点被驱动到第一或第二充电状态。对于一个充电状态，电荷存储信号通过晶体管（64）和电容器（68）被选通到浮动栅极节点（44）。电荷通过包括在单晶衬底上制造的电介质的电流隧穿元件（48,50）传送到浮栅节点（44）。对于调用操作，将调用命令信号施加到将晶体管（42）耦合到易失性存储器电路的＆amp; D＆D节点（22）的晶体管（52）。如果正电荷状态已经存储在电荷存储节点（44）处，晶体管（42）被导通以将＆amp;上升＆D节点（22）拉到地，以将数据状态恢复到易失性存储器电路。如果在电荷存储节点（44）处存储了负电荷状态，则没有负载施加到DATA节点（20）或者＆amp; Upbar＆D节点（22）上。交叉耦合晶体管（12,14）被制造成具有不同的长度，使得每当遇到默认条件时，节点（22）被驱动到高电压状态，从而将原始数据状态恢复到易失性存储器电路。

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