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11. 发明授权

US08230178B2 Data processing system and method for efficient coherency communication utilizing coherency domain indicators 有权
标题翻译：数据处理系统和方法，利用相干域指标进行有效的一致性通信
公开(公告)号：US08230178B2
公开(公告)日：2012-07-24
申请号：US11055483
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0826
摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.
摘要翻译：在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内域。第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播系统按照确定。

12. 发明授权

US07689777B2 Cache member protection with partial make MRU allocation 失效
标题翻译：缓存成员保护部分使MRU分配
公开(公告)号：US07689777B2
公开(公告)日：2010-03-30
申请号：US11951770
申请日：2007-12-06
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译：一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。保护位用作用于标识要保护的同余类的成员的位置的指针。在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下，否定受保护成员的选择。

13. 发明授权

US07584329B2 Data processing system and method for efficient communication utilizing an Ig coherency state 失效
标题翻译：数据处理系统和利用Ig一致性状态的高效通信方法
公开(公告)号：US07584329B2
公开(公告)日：2009-09-01
申请号：US11055524
申请日：2005-02-10
申请人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元和高速缓冲存储器。高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。一致性状态字段具有多个可能的状态，包括指示地址标签有效的状态，存储位置不包含有效数据，并且存储器块可能被高速缓存在第一相干域之外。

14. 发明申请

US20080177953A1 CACHE MEMBER PROTECTION WITH PARTIAL MAKE MRU ALLOCATION 失效
标题翻译：缓存成员保护，部分成为MRU分配
公开(公告)号：US20080177953A1
公开(公告)日：2008-07-24
申请号：US11951770
申请日：2007-12-06
申请人： ROBERT H. BELL , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： ROBERT H. BELL , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/12
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译：一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。保护位用作用于标识要保护的同余类的成员的位置的指针。在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下否定对被保护成员的选择。

15. 发明授权

US07401189B2 Pipelining D states for MRU steerage during MRU/LRU member allocation 失效
标题翻译：在MRU / LRU成员分配过程中，管理MRU操纵的D状态
公开(公告)号：US07401189B2
公开(公告)日：2008-07-15
申请号：US11054067
申请日：2005-02-09
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0888 , G06F12/123 , G06F12/126 , G06F2212/1032
摘要： A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.
摘要翻译：用于在LRU受害者选择期间防止选择被删除（D）成员作为LRU受害者的方法和装置。在针对特定同余类的每个缓存访问期间，从高速缓存目录中的信息识别已删除的高速缓存行。删除的高速缓存行的位置在LRU受害者选择期间通过高速缓存架构流水线化。信息被锁存，然后传递给MRU向量生成逻辑。生成MRU向量并将其传递给MRU更新逻辑，MRU更新逻辑是将删除的成员作为MRU成员进行选择/标记。使MRU操作仅影响以基于树的结构状态位布置的较低级LRU状态位，使得MRU操作仅在D状态下否定特定成员的选择，而不影响其他成员的LRU受害者选择。

16. 发明申请

US20090006758A1 SYSTEM BUS STRUCTURE FOR LARGE L2 CACHE ARRAY TOPOLOGY WITH DIFFERENT LATENCY DOMAINS 失效
公开(公告)号：US20090006758A1
公开(公告)日：2009-01-01
申请号：US12207393
申请日：2008-09-09
申请人： Vicente Enrique Chung , Guy Lynn Guthrie , Willliam John Starke , Jeffrey Adam Stuecheli
发明人： Vicente Enrique Chung , Guy Lynn Guthrie , Willliam John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0851 , Y02D10/13
摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses.

17. 发明授权

US08352712B2 Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted 失效
标题翻译：方法和系统，用于将处理器发出的存储操作特定发送到存储队列，并发出全信号
公开(公告)号：US08352712B2
公开(公告)日：2013-01-08
申请号：US10840560
申请日：2004-05-06
申请人： Robert H. Bell, Jr. , Thomas Michael Capasso , Guy Lynn Guthrie , Hugh Shen , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Thomas Michael Capasso , Guy Lynn Guthrie , Hugh Shen , Jeffrey Adam Stuecheli
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/3861
摘要： A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store operations while the store queue full signal is asserted. A copy of the speculatively issued store operation is placed within a speculative store buffer. The core waits for a signal from the store queue indicating the store operation was accepted into the store queue. When the speculatively-issued store operation is accepted within the store queue, the copy is discarded from the buffer. However, when the store operation is rejected, the speculative store logic re-issues the store operation ahead of normal store operations.
摘要翻译：一种方法和处理器芯片设计，用于使得处理器核心能够在核心接收到存储队列已满的指示之后继续向商店队列发送存储操作。处理器核心配置有推测存储逻辑，使得处理器核心能够在存储队列满信号被断言的同时继续发出存储操作。投机发行的存储操作的副本放置在推测性存储缓冲区内。核心等待来自存储队列的信号，指示存储操作被接受到存储队列中。当存储队列中接受推测发出的存储操作时，该副本将从缓冲区中丢弃。然而，当存储操作被拒绝时，推测存储逻辑在正常存储操作之前重新发布存储操作。

18. 发明授权

US06493814B2 Reducing resource collisions associated with memory units in a multi-level hierarchy memory system 失效
公开(公告)号：US06493814B2
公开(公告)日：2002-12-10
申请号：US09801610
申请日：2001-03-08
申请人： James Stephen Fields, Jr. , Jody Bern Joyner , William John Starke , Jeffrey Adam Stuecheli
发明人： James Stephen Fields, Jr. , Jody Bern Joyner , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F1200
CPC分类号： G06F12/0811
摘要： A system and method for reducing resource collisions associated with memory units. Resource collisions may be reduced in part by a hash that combines the number N bits in the bank selector field with the number M bits adjacent to a region of correlation, e.g., row selector field, in an address to determine which bank in a memory unit, e.g., cache, may store the information associated with the address.

19. 发明授权

US07840758B2 Variable store gather window 有权
标题翻译：变量存储收集窗口
公开(公告)号：US07840758B2
公开(公告)日：2010-11-23
申请号：US11689990
申请日：2007-03-22
申请人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
发明人： Robert H. Bell, Jr. , Hugh Shen , Jeffrey Adam Stuecheli , Derek Edward Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F12/0897
摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.
摘要翻译：处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

20. 发明授权

US07380066B2 Store stream prefetching in a microprocessor 失效
标题翻译：在微处理器中存储流预取
公开(公告)号：US07380066B2
公开(公告)日：2008-05-27
申请号：US11054871
申请日：2005-02-10
申请人： John Barry Griswell, Jr. , Hung Qui Le , Francis Patrick O'Connell , William J. Starke , Jeffrey Adam Stuecheli , Albert Thomas Williams
发明人： John Barry Griswell, Jr. , Hung Qui Le , Francis Patrick O'Connell , William J. Starke , Jeffrey Adam Stuecheli , Albert Thomas Williams
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/30047 , G06F9/383 , G06F12/0811
摘要： In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2M contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.
摘要翻译：在具有加载/存储单元和预取硬件的微处理器中，预取硬件包括预取队列，其包含指示分配的数据流的条目。预取引擎接收与由加载/存储单元执行的存储指令相关联的地址。预取引擎通过将队列中的条目与包含多个高速缓存块的地址的窗口进行比较来确定是否对与存储指令相对应的预取队列中的条目进行分配，其中地址窗口从接收到的地址导出。预取引擎将预取队列中的条目与两个连续高速缓存块的窗口进行比较。当预取队列中的任何条目都在地址窗口内时，预取引擎抑制新条目的分配。当存储指令的数据地址等于地址窗口的边界区域中的地址时，预取引擎进一步抑制新条目的分配。

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