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11. 发明授权

US07903687B2 Method for scheduling, writing, and reading data inside the partitioned buffer of a switch, router or packet processing device 失效
标题翻译：在交换机，路由器或分组处理设备的分区缓冲区内调度，写入和读取数据的方法
公开(公告)号：US07903687B2
公开(公告)日：2011-03-08
申请号：US11096363
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04J3/16 , H04J3/22 , H04J3/24
CPC分类号： H04L49/901 , H04J3/0632 , H04L47/50 , H04L49/90 , H04L49/9031
摘要： A method for receiving packets in a computer network are disclosed. The method include providing at least one receive port, a buffer, a scheduler, and a wrap port. The buffer has an input coupled with the at least one receive port and an output. The scheduler has a first input coupled to the output of the buffer, a second input coupled to the wrap port, and an output.
摘要翻译：公开了一种在计算机网络中接收分组的方法。该方法包括提供至少一个接收端口，缓冲器，调度器和包装端口。缓冲器具有与至少一个接收端口和输出端耦合的输入。调度器具有耦合到缓冲器的输出的第一输入，耦合到包装端口的第二输入和输出。

12. 发明授权

US07706409B2 System and method for parsing, filtering, and computing the checksum in a host Ethernet adapter (HEA) 有权
标题翻译：在主机以太网适配器（HEA）中解析，过滤和计算校验和的系统和方法
公开(公告)号：US07706409B2
公开(公告)日：2010-04-27
申请号：US11096365
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04J3/24
CPC分类号： H04L1/0052 , H04L1/0061
摘要： A system and method for parsing, filtering, and computing the checksum in a host Ethernet adapter (HEA) that is coupled to a host. The method includes receiving a part of a frame, wherein a plurality of parts of a frame constitute a entire frame. Next, parse the part of a frame before receiving the entire frame. The HEA computes a checksum of the part of a frame. The HEA filters the part of a frame based on a logical, port-specific policy and transmits the checksum to the host.
摘要翻译：用于在耦合到主机的主机以太网适配器（HEA）中解析，过滤和计算校验和的系统和方法。该方法包括接收帧的一部分，其中帧的多个部分构成整个帧。接下来，在接收整个帧之前解析帧的一部分。 HEA计算帧的一部分的校验和。 HEA基于逻辑，端口特定策略过滤帧的一部分，并将校验和传送到主机。

13. 发明授权

US07508771B2 Method for reducing latency in a host ethernet adapter (HEA) 失效
标题翻译：用于减少主机以太网适配器（HEA）中的延迟的方法
公开(公告)号：US07508771B2
公开(公告)日：2009-03-24
申请号：US11096353
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04L12/26
CPC分类号： H04L12/413 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/22 , H04L69/324
摘要： A method for reducing latency in a host Ethernet adapter (HEA) includes the following. First, the HEA receives a packet with an internet protocol (IP) header and data in the HEA. The HEA parses a connection identifier from the IP header and accesses a negative cache in the HEA to determine if the connection identifier is not in a memory external to the HEA. The HEA applies a default treatment to the packet if the connection identifier is not in the memory, thereby reducing latency by decreasing access to the memory.
摘要翻译：一种用于减少主机以太网适配器（HEA）中的延迟的方法包括以下。首先，HEA在HEA中接收到具有互联网协议（IP）头部和数据的分组。 HEA从IP头解析连接标识符，并访问HEA中的负缓存，以确定连接标识符是否不在HEA外部的存储器中。如果连接标识符不在存储器中，则HEA对数据包应用默认处理，从而通过减少对存储器的访问来减少延迟。

14. 发明授权

US07782888B2 Configurable ports for a host ethernet adapter 有权
标题翻译：主机以太网适配器的可配置端口
公开(公告)号：US07782888B2
公开(公告)日：2010-08-24
申请号：US11953820
申请日：2007-12-10
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
IPC分类号： H04L12/28
CPC分类号： H04L12/40032 , H04L12/413 , H04L49/90 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/18 , H04L69/323 , H04L69/324
摘要： A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
摘要翻译：根据本发明的系统和方法允许在可以使用相同引脚容纳10G和1G源的服务器环境中使用适配器。这是通过使用可以容纳两个数据源的高速串行器/解串器（高速serdes）来实现的。高速serdes允许在NIC上使用相对较低的参考时钟速度来提供数据源的适当时钟，并且还允许设置不同的模式以适应不同的数据源。最后，该系统允许适配器为多个数据源使用相同的引脚。

15. 发明授权

US07409520B2 Systems and methods for time division multiplex multithreading 失效
标题翻译：时分复用多线程的系统和方法
公开(公告)号：US07409520B2
公开(公告)日：2008-08-05
申请号：US11042692
申请日：2005-01-25
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

16. 发明授权

US07953951B2 Systems and methods for time division multiplex multithreading 失效
标题翻译：时分复用多线程的系统和方法
公开(公告)号：US07953951B2
公开(公告)日：2011-05-31
申请号：US12124396
申请日：2008-05-21
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

17. 发明授权

US07469332B2 Systems and methods for adaptively mapping an instruction cache 失效
标题翻译：用于自适应地映射指令高速缓存的系统和方法
公开(公告)号：US07469332B2
公开(公告)日：2008-12-23
申请号：US11070758
申请日：2005-03-02
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Harm Peter Hofstee , Jens Leenstra , Hans-Werner Tast , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Harm Peter Hofstee , Jens Leenstra , Hans-Werner Tast , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F9/355
CPC分类号： G06F12/0864
摘要： Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for observing collisions that occur for a given mapping of system memory bits into a tag and an index. Based on the observations, an optimal mapping may be determined that minimizes collisions.
摘要翻译：公开了用于将系统存储器地址位自适应地映射到指令标签和到高速缓存中的索引的系统和方法。更具体地，公开了用于观察对于系统存储器位给定到标签和索引的映射而出现的冲突的硬件和软件。基于观察结果，可以确定最小化碰撞的最佳映射。

18. 发明申请

US20080222394A1 Systems and Methods for TDM Multithreading 失效
标题翻译： TDM多线程的系统和方法
公开(公告)号：US20080222394A1
公开(公告)日：2008-09-11
申请号：US12124396
申请日：2008-05-21
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor David , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor David , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

19. 发明授权

US07474662B2 Systems and methods for rate-limited weighted best effort scheduling 失效
标题翻译：速率限制加权最佳努力调度的系统和方法
公开(公告)号：US07474662B2
公开(公告)日：2009-01-06
申请号：US11119329
申请日：2005-04-29
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L47/623 , H04L47/50 , H04L47/568
摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a four-entry calendar structure provides for rate-limited weighted best effort scheduling. Each of a plurality of different flows has associated schedule control blocks. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a rate limit according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its rate limit, the schedule control block is temporarily removed from further scheduling until a time interval concludes.
摘要翻译：公开了一种用于在网络处理器中调度数据分组的系统和方法。实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。在一个实施例中，四入口日历结构提供速率受限加权最佳努力调度。多个不同流中的每一个都具有相关联的调度控制块。计划控制块作为链表存储在先进先出缓冲区中。通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。每个调度控制块都有一个计数器，并根据相应数据包所属的流的带宽优先级分配速率限制。每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。当调度控制块的递增计数器等于其速率限制时，调度控制块暂时从进一步调度中移除，直到时间间隔结束。

20. 发明授权

US07529224B2 Scheduler, network processor, and methods for weighted best effort scheduling 失效
标题翻译：调度器，网络处理器和加权最佳努力调度的方法
公开(公告)号：US07529224B2
公开(公告)日：2009-05-05
申请号：US11108485
申请日：2005-04-18
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L47/568 , H04L45/00 , H04L45/60 , H04L47/50 , H04L47/527
摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a three-entry calendar structure provides for weighted best effort scheduling. Each of a plurality different flows has an associated schedule control block. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a weight according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its weight, the schedule control block is temporarily removed from further scheduling.
摘要翻译：公开了一种用于在网络处理器中调度数据分组的系统和方法。实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。在一个实施例中，三入口日历结构提供加权最佳努力调度。多个不同的流中的每一个具有相关的进度控制块。计划控制块作为链表存储在先进先出缓冲区中。通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。每个调度控制块具有计数器，并根据相应分组所属的流的带宽优先级分配权重。每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。当调度控制块的递增计数器等于其权重时，调度控制块暂时从进一步调度中移除。

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