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11. 发明申请

US20050018401A1 Device for cooling memory modules 失效
标题翻译：用于冷却内存模块的设备
公开(公告)号：US20050018401A1
公开(公告)日：2005-01-27
申请号：US10829362
申请日：2004-04-22
申请人： Christian Stocken , Stephan Schroder , Thomas Huber , Manfred Proll
发明人： Christian Stocken , Stephan Schroder , Thomas Huber , Manfred Proll
IPC分类号： G06F1/20 , H01L23/367 , H01L23/433 , H05K7/20
CPC分类号： H01L23/367 , G06F1/20 , H01L23/4338 , H01L2924/0002 , H01L2924/00
摘要： A device for cooling memory modules can include a plurality of elements. The elements can thermal couple at least two memory modules. The device can further include a body or a plurality of contact areas bearing in a planar manner.
摘要翻译：用于冷却存储器模块的装置可以包括多个元件。元件可以热耦合至少两个存储器模块。该装置还可包括以平面方式支承的主体或多个接触区域。

12. 发明申请

US20050194614A1 Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory 失效
标题翻译：集成半导体存储器和用于电应力集成半导体存储器的方法
公开(公告)号：US20050194614A1
公开(公告)日：2005-09-08
申请号：US11061087
申请日：2005-02-18
申请人： Georg Eggers , Stephan Schroder , Manfred Proll , Herbert Benzinger
发明人： Georg Eggers , Stephan Schroder , Manfred Proll , Herbert Benzinger
IPC分类号： G11C11/407 , G11C29/00 , G11C29/02 , H01L21/66 , H01L21/8242 , H01L27/10 , H01L27/105 , H01L29/73 , H01L29/739 , H01L29/74
CPC分类号： G11C29/025 , G11C29/02 , H01L27/105 , H01L27/10891
摘要： Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, 15b) coupled to the main word line (10a, 10b), which are coupled to the respective main word line (10a, 10b) in each case via at least one contact hole filling (11). If one of the contact hole fillings (11) is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments (15a, 15b) of two respective word lines (5a, 5b) can be short-circuited in pairs with the aid of switching units (20), whereby a static current (I) that flows via the contact hole fillings (11) can be used for electrically stressing the contact hole fillings (11). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.
摘要翻译：半导体存储器（1）具有分段字线（5a，5b），其在每种情况下具有由导电金属制成的主字线（10a，10b）和多个互连片段（15a，15b）），其耦合到主字线（10a，10b），其通过至少一个接触孔填充物（11）在每种情况下耦合到相应的主字线（10a，10b）。如果接触孔填充物（11）中的一个有缺陷或高电阻，则会发生半导体存储器的功能错误。两个相应字线（5a，5b）的互连段（15a，5b）可以借助于开关单元（20）成对地短路，由此通过接触孔填充物（11）可以用于电接触接触孔填充物（11）。因此，分段字线的接触孔填充的电应力成为可能。

13. 发明授权

US4960374A Apparatus for molding outer and inner soles and a sole welt onto shoe uppers 失效
标题翻译：用于成型外鞋底和鞋底的鞋底和鞋底上的鞋底
公开(公告)号：US4960374A
公开(公告)日：1990-10-02
申请号：US340270
申请日：1989-04-19
申请人： Manfred Proll
发明人： Manfred Proll
IPC分类号： B29D35/00 , B29C45/14 , B29D35/08 , B29K105/20 , B29L31/50
CPC分类号： B29D35/082
摘要： Outer and inner soles and a sole welt are molded onto shoe uppers. A molded outer sole is formed by injection molding plasticized thermoplastic material into a first mold cavity defined by a first mold part at an end of a pivotable mold carrier and a confronting mold plate. A molded sole welt closed on itself is formed on a last supported shoe upper by injection molding plasticized thermoplastic material into a sole welt mold cavity defined by an opposed pair of first lateral mold elements closed against the shoe upper while a second mold part at an opposite end of the mold carrier confronts the shoe upper and the lateral mold elements. The mold carrier is shifted away from the lateral mold elements and pivoted to confront the first mold part and the molded outer sole to the shoe upper. An inner sole mold cavity is formed with the molded outer sole by closing an opposed pair of second lateral mold elements located between the first lateral elements and the first mold part. A molded inner sole is formed by injection molding foamed plasticized thermoplastic material into the inner sole mold cavity. The molded outer sole may be formed by separately injection molding plasticized thermoplastic material into portions of the first mold cavity during first and second steps of the first molding cycle.
摘要翻译：外鞋底和鞋底均匀地镶嵌在鞋面上。通过将可塑化的热塑性材料注塑成由可枢转模具托架的端部和相对的模具板的第一模具部件限定的第一模具腔体而形成模制的外底部。通过将增塑的热塑性材料注射成型而成的鞋底边缘模腔中，在最后一个支撑的鞋面上形成一个封闭的模制底部边缘，该底部边缘模具腔由相对的一对第一侧向模具元件限定，模具承载件的端部面对鞋面和侧面模具元件。模具托架从侧面模具元件移开并且枢转以面对第一模具部件和模制的外底部到鞋面。通过闭合位于第一侧向元件和第一模具部件之间的相对的一对第二侧模元件，形成具有模制的外底的内单模模腔。通过将泡沫塑化的热塑性材料注塑成内层模具腔形成模制内底。模制的外底可以通过在第一模制周期的第一和第二步骤期间将增塑的热塑性材料分别注塑成第一模腔的部分而形成。

14. 发明申请

US20050041519A1 Integrated clock supply chip for a memory module, memory module comprising the integrated clock supply chip, and method for operating the memory module under test conditions 有权
标题翻译：用于存储器模块的集成时钟供应芯片，包括集成时钟供应芯片的存储器模块以及用于在测试条件下操作存储器模块的方法
公开(公告)号：US20050041519A1
公开(公告)日：2005-02-24
申请号：US10886523
申请日：2004-07-07
申请人： Nazif Taskin , Manfred Proll , Manfred Dobler , Gerald Resch
发明人： Nazif Taskin , Manfred Proll , Manfred Dobler , Gerald Resch
IPC分类号： G11C7/22 , G11C11/4076 , G11C29/14 , G11C8/18
CPC分类号： G11C29/12015 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C29/14
摘要： The integrated chip according to the invention has a clock signal input (1.1) for application of a first clock signal (clk1) and a clock signal output (1.2-1.5). Moreover, it has a phase locked loop (2), which, on the input side, is connected to the clock signal input (1.1) and serves for generating a second clock signal (clk2). Furthermore, the chip has a multiplexer (MUX), via which the first clock signal (clk1) or the second clock signal (clk2) can optionally be switched to the clock signal output (1.2-1.5), and a unit for frequency monitoring (3), which, on the input side, is connected to the clock signal input (1.1) and is designed and can be operated in such a way that, in the event of a limiting frequency (fmin) being undershot, the multiplexer (MUX) is caused to switch the first clock signal (clk1) to the clock signal output (1.2-1.5).
摘要翻译：根据本发明的集成芯片具有用于施加第一时钟信号（clk1）和时钟信号输出（1.2-1.5）的时钟信号输入（1.1）。此外，它具有锁相环（2），其在输入侧连接到时钟信号输入端（1.1）并用于产生第二时钟信号（clk2）。此外，芯片具有多路复用器（MUX），第一时钟信号（clk1）或第二时钟信号（clk2）可以选择地切换到时钟信号输出（1.2-1.5），以及用于频率监视的单元 3），其在输入侧连接到时钟信号输入（1.1），并且被设计并且可以以这样的方式操作，使得在频率（fmin）不足的情况下，多路复用器（MUX ）将第一个时钟信号（clk1）切换到时钟信号输出（1.2-1.5）。

15. 发明授权

US4810178A Apparatus for molding outer and inner soles onto shoe uppers 失效
标题翻译：用于将外鞋底和内鞋底成型到鞋面上的装置
公开(公告)号：US4810178A
公开(公告)日：1989-03-07
申请号：US116666
申请日：1987-11-04
申请人： Manfred Proll , Gunter Rebers
发明人： Manfred Proll , Gunter Rebers
IPC分类号： B29D35/08 , B29C45/16
CPC分类号： B29D35/082 , B29D35/087
摘要： An apparatus for molding an outer sole of elastomer and an inner sole of a mixture of isocyanate and a polyol reacting into polyurethane to shoe uppers includes a vertically movable upper cross block supporting a pivotably mounted mold carrier with a heatable first mold part at one end for the molding of outer soles, and a lower, vertically adjustable cross block has a heatable plate in contact with the first mold part. The mold carrier is pivoted such that the heatable first mold part containing the molded outer sole forms a mold cavity for an inner sole together with laterally movable mold elements and a last supported shoe upper. A vertically adjustable last body has a transfer plate which transfers the molded outer sole from the heatable first mold part for cooling before the molded outer sole is transferred back to a cooled mold part at the opposite end of the mold carrier, after which the last supported shoe upper is rotated to confront the outer sole and the lateral mold elements are closed to define a cavity for the molding of the inner sole.
摘要翻译：用于模制弹性体外底的装置和反应成聚氨酯至鞋面的异氰酸酯和多元醇的混合物的内底的装置包括可垂直运动的上横向块，其支撑可枢转地安装的模具架，其一端具有可加热的第一模具部件外底的成型和下部可垂直调节的交叉块具有与第一模具部分接触的可加热板。模具托架枢转，使得包含模制的外底的可加热的第一模具部件与侧向可移动的模具元件和最后支撑的鞋面形成用于内底的模腔。可垂直调节的最后一个主体具有转印板，该转印板将模制的外底从可加热的第一模具部件转移以进行冷却，然后将模制的外底转移回模具架的相对端处的冷却的模具部件，之后最后支撑鞋面被旋转以面对外底，并且侧模元件被关闭以限定用于内底的模制的空腔。

16. 发明申请

US20050249016A1 Method for testing an integrated semiconductor memory 有权
标题翻译：用于测试集成半导体存储器的方法
公开(公告)号：US20050249016A1
公开(公告)日：2005-11-10
申请号：US11121175
申请日：2005-05-04
申请人： Koen van Zanden , Manfred Proll , Jorg Kliewer , Bjorn Wirker
发明人： Koen van Zanden , Manfred Proll , Jorg Kliewer , Bjorn Wirker
IPC分类号： G11C7/12 , G11C8/00 , G11C11/4091 , G11C29/00 , G11C29/50
CPC分类号： G11C29/50 , G11C11/401 , G11C29/12015 , G11C29/50012 , G11C2029/1204 , G11C2029/2602
摘要： An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven synchronously with a clock edge of the control clock with a first control signal and starts a test run independent of the control clock. Driving with the first control signal, selection transistors in a memory bank that can be selected by a memory bank address are turned off. Afterward, bit lines in the selected memory bank are interconnected and driven with a predetermined precharge potential. After a precharge time has elapsed, one of the word lines is selected by an applied word line address and the selection transistors in the selected memory bank connected to the selected word line are turned on. Precharge times are set and tested independently of the clock period of the control clock.
摘要翻译：集成半导体存储器可以在与控制时钟同步的正常操作状态下操作。在测试操作状态下，集成半导体存储器与第一控制信号的控制时钟的时钟边沿同步地驱动，并独立于控制时钟启动测试运行。利用第一控制信号驱动，可以由存储体地址选择的存储体中的选择晶体管截止。之后，所选择的存储体中的位线被互连并以预定的预充电势驱动。在预充电时间过去之后，通过应用的字线地址选择一个字线，并且连接到所选字线的所选存储体中的选择晶体管导通。独立于控制时钟的时钟周期设置和测试预充电时间。

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