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11. 再颁专利

USRE41561E1 Method for sharing configuration data for high logic density on chip 有权
标题翻译：用于共享芯片上高逻辑密度的配置数据的方法
公开(公告)号：USRE41561E1
公开(公告)日：2010-08-24
申请号：US12110205
申请日：2008-04-25
申请人： Ankur Bal
发明人： Ankur Bal
IPC分类号： H01L25/00
CPC分类号： H03K19/17728
摘要： A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.
摘要翻译：提供了一种用于减少实现布尔函数所需的查找表中可编程体系结构元素数量或相同或逻辑等价的操作的系统。该系统可以包括连接到多个解码器的输入的单组存储元件，并且存储元件可以由解码器同时访问以向其提供同时多个输出。

12. 发明授权

US07180792B2 Efficient latch array initialization 有权
标题翻译：高效的锁存器阵列初始化
公开(公告)号：US07180792B2
公开(公告)日：2007-02-20
申请号：US10377297
申请日：2003-02-28
申请人： Ankur Bal , Manish Agarwal
发明人： Ankur Bal , Manish Agarwal
IPC分类号： G11C7/10
CPC分类号： H03K19/17776 , G11C7/20 , H03K19/1776 , H03K19/17772 , H03K19/1778
摘要： An efficient method and electronic circuit for initializing latch arrays in an electronic device including an FPGA and a memory device includes a group of one or more data latches, each including a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring significant additional circuitry.
摘要翻译：一种用于在包括FPGA和存储器件的电子设备中初始化锁存器阵列的有效方法和电子电路包括一组一个或多个数据锁存器，每个数据锁存器包括一对交叉耦合的反相逻辑元件，其特征在于，它包括一个装置用于同时将每个数据锁存器初始化为预定的逻辑状态，而不需要显着的附加电路。

13. 发明授权

US07030648B2 High performance interconnect architecture for field programmable gate arrays 有权
标题翻译：用于现场可编程门阵列的高性能互连架构
公开(公告)号：US07030648B2
公开(公告)日：2006-04-18
申请号：US10739395
申请日：2003-12-18
申请人： Ankur Bal , Namerita Khanna
发明人： Ankur Bal , Namerita Khanna
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： This invention relates to a high performance interconnect architecture providing reduced delay minimized electro-migration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.
摘要翻译：本发明涉及一种高性能互连架构，其提供减少的延迟最小化的电迁移和FPGA中的减少的区域，包括由互连的逻辑块组成的多个瓦片，其由中间的逻辑块分隔。每组相互连接的逻辑块由互连段链接，该互连段通过互连层在中间逻辑块上以直线路由，并且通过连接段选择性地连接到每端的逻辑块。

14. 发明授权

US07038489B2 Method for sharing configuration data for high logic density on chip 有权
公开(公告)号：US07038489B2
公开(公告)日：2006-05-02
申请号：US10172355
申请日：2002-06-14
申请人： Ankur Bal
发明人： Ankur Bal
IPC分类号： H01L25/00
CPC分类号： H03K19/17728
摘要： A system for reducing the number of programmable architecture elements in a look-up table required for implementing Boolean functions or operations that are identical or logically equivalent is provided. The system may include a single set of storage elements connected to the inputs of multiple decoders, and the storage elements may be concurrently accessed by the decoders to provide simultaneous multiple outputs thereto.

15. 发明授权

US06624771B2 Concurrent logic operations using decoder circuitry of a look-up table 有权
标题翻译：使用查找表的解码器电路的并行逻辑运算
公开(公告)号：US06624771B2
公开(公告)日：2003-09-23
申请号：US10145390
申请日：2002-05-14
申请人： Ankur Bal
发明人： Ankur Bal
IPC分类号： H03M700
CPC分类号： H03K19/17728
摘要： A look-up table circuit includes address decoder circuitry that includes circuitry for utilizing the address decoder circuitry for producing secondary functions concurrently with operation of the address decoding operations. This eliminates or reduces additional circuitry required for generating the secondary functions.
摘要翻译：查找表电路包括地址解码器电路，其包括用于利用地址解码器电路与地址解码操作的操作同时产生辅助功能的电路。这消除或减少了生成次要功能所需的附加电路。

16. 发明授权

US06888374B2 FPGA peripheral routing with symmetric edge termination at FPGA boundaries 有权
标题翻译：在FPGA边界处具有对称边缘终止的FPGA外围设备路由
公开(公告)号：US06888374B2
公开(公告)日：2005-05-03
申请号：US10464420
申请日：2003-06-17
申请人： Ankur Bal
发明人： Ankur Bal
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17796
摘要： An FPCA includes a scheme for peripheral routing that provides symmetrical routing across its entire area including the periphery by incorporating peripheral routing lines of equal length that are symmetrically deflected orthogonally. The symmetrical peripheral routing lines are connected to switch boxes and connection boxes at the periphery for maintaining constant routing channel width.
摘要翻译： FPCA包括用于外围路由的方案，其通过并入正交对称偏转的相等长度的外围路由线来提供包括外围在内的整个区域的对称路由。对称的外围路由线路连接到外围的交换机和连接盒，以保持不断的路由信道宽度。

17. 发明授权

US06748577B2 System for simplifying the programmable memory to logic interface in FPGA 有权
标题翻译：用于简化FPGA中可编程存储器到逻辑接口的系统
公开(公告)号：US06748577B2
公开(公告)日：2004-06-08
申请号：US10186314
申请日：2002-06-28
申请人： Ankur Bal
发明人： Ankur Bal
IPC分类号： G06F1750
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/17744
摘要： A system for simplifying the programmable memory-to-logic interface in field programmable gate arrays (FPGAs) is provided. An interface may be used to isolate the general purpose routing architecture for intra-programmable logic blocks (PLBs) from the random access memory (RAM) address lines, data lines, and control lines. The PLBs and the input-output resources of the FPGA access the embedded memory (or RAM) using dedicated direct interconnects. Certain of these direct interconnects may originate from PLBs in the vicinity of the RAM. The remainder run between the input-output (IO) pads/routing and the RAM blocks. A bus routing architecture is also provided to combine the memories to emulate larger RAM blocks. This bus routing provides interconnection among RAM blocks and is isolated from the PLB routing resources.
摘要翻译：提供了一种用于简化现场可编程门阵列（FPGA）中的可编程存储器到逻辑接口的系统。可以使用接口来隔离来自随机存取存储器（RAM）地址线，数据线和控制线的可编程逻辑块（PLB）的通用路由架构。 FPGA的PLB和输入输出资源使用专用直接互连访问嵌入式存储器（或RAM）。这些直接互连中的某些可能来自RAM附近的PLB。剩余部分在输入 - 输出（IO）焊盘/路由和RAM块之间运行。还提供总线路由架构以组合存储器以模拟较大的RAM块。该总线路由提供RAM块之间的互连，并与PLB路由资源隔离。

18. 发明授权

US11336194B1 DC-AC converter 有权
公开(公告)号：US11336194B1
公开(公告)日：2022-05-17
申请号：US17221905
申请日：2021-04-05
申请人： Vikram Singh , Ankur Bal , Vineet Mehta , Jitender Singh
发明人： Vikram Singh , Ankur Bal , Vineet Mehta , Jitender Singh
IPC分类号： H02M7/42 , H02M3/335 , H02M1/12
摘要： Disclosed herein is a DC-AC converter, in accordance with some embodiments. Accordingly, the DC-AC converter comprises a transformer, a pulse generator, a pulse modulator, a switching element, and an analog low pass filtering stage. Further, the pulse generator is configured for generating pulses characterized by a pulse frequency. Further, the pulse modulator is configured for generating a pulse density modulated signal based on modulating the pulses using a sine wave signal of a fundamental frequency. Further, the switching element is connected in series with a primary winding of the transformer. Further, the switching element is configured to be switched between an on state and an off state based on the pulse density modulated signal. Further, the analog low pass filtering stage is configured for generating an AC voltage of the fundamental frequency based on attenuating higher frequency components of an unfiltered AC voltage at a secondary winding of the transformer.

19. 发明授权

US07856467B2 Integrated circuit including at least one configurable logic cell capable of multiplication 有权
标题翻译：集成电路包括能够乘法的至少一个可配置逻辑单元
公开(公告)号：US07856467B2
公开(公告)日：2010-12-21
申请号：US11324019
申请日：2005-12-29
申请人： Parvesh Swami , Ankur Bal
发明人： Parvesh Swami , Ankur Bal
IPC分类号： G06F7/52
CPC分类号： G06F7/523 , G06F7/5312
摘要： The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial product at its second input with its select line being controlled by second input, said first multiplexing means providing a first output; and a second multiplexing means for receiving a second output of said addition means at its first input and said second input at its second input with its select line being coupled to said second input, said second multiplexing means providing a second output.
摘要翻译：本发明提供了一种集成电路，其包括能够进行乘法的至少一个可配置逻辑单元，该逻辑单元包括用于添加第一输入和部分乘积的加法装置; 第一多路复用装置，用于在其第一输入处接收所述加法装置的第一输出，在其第二输入处接收所述部分乘积，其选择线由第二输入控制，所述第一多路复用装置提供第一输出; 以及第二多路复用装置，用于在其第一输入处接收所述加法装置的第二输出，在其第二输入处接收所述第二输入，其选择线耦合到所述第二输入，所述第二多路复用装置提供第二输出。

20. 发明申请

US20060195503A1 Integrated circuit including at least one configurable logic cell capable of multiplication 有权
标题翻译：集成电路包括能够乘法的至少一个可配置逻辑单元
公开(公告)号：US20060195503A1
公开(公告)日：2006-08-31
申请号：US11324019
申请日：2005-12-28
申请人： Parvesh Swami , Ankur Bal
发明人： Parvesh Swami , Ankur Bal
IPC分类号： G06F7/52
CPC分类号： G06F7/523 , G06F7/5312
摘要： The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial product at its second input with its select line being controlled by second input, said first multiplexing means providing a first output; and a second multiplexing means for receiving a second output of said addition means at its first input and said second input at its second input with its select line being coupled to said second input, said second multiplexing means providing a second output.
摘要翻译：本发明提供了一种集成电路，其包括能够进行乘法的至少一个可配置逻辑单元，该逻辑单元包括用于添加第一输入和部分乘积的加法装置; 第一多路复用装置，用于在其第一输入处接收所述加法装置的第一输出，在其第二输入处接收所述部分乘积，其选择线由第二输入控制，所述第一多路复用装置提供第一输出; 以及第二多路复用装置，用于在其第一输入处接收所述加法装置的第二输出，在其第二输入处接收所述第二输入，其选择线耦合到所述第二输入，所述第二多路复用装置提供第二输出。

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