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11. 发明申请

US20050228844A1 Fast operand formatting for a high performance multiply-add floating point-unit 审中-公开
标题翻译：用于高性能乘法加法浮点单元的快速操作数格式化
公开(公告)号：US20050228844A1
公开(公告)日：2005-10-13
申请号：US10821606
申请日：2004-04-08
申请人： Sang Dhong , Silvia Mueller , Hiroo Nishikawa , Hwa-Joon Oh
发明人： Sang Dhong , Silvia Mueller , Hiroo Nishikawa , Hwa-Joon Oh
IPC分类号： G06F7/38 , G06F7/483 , G06F7/544 , G06F7/57
CPC分类号： G06F7/483 , G06F7/5443
摘要： Disclosed are a floating point execution unit, and a method of operating a floating point unit, to perform multiply/add operations using a plurality of operands from an instruction having a plurality of operand positions. The floating point unit comprises a multiplier for calculating a product of two of the operands, and an aligner for combining said product and a third of the operands. A first data path is used to supply to the multiplier operands from a first and a second of the operand positions of the instruction, and a second data path is used to supply the third operand to the aligner. The floating point unit further comprises a multiplexer on the second data path for selecting, for use by the aligner, either the operand from the second operand position or the operand from the third operand position of the instruction.
摘要翻译：公开了一种浮点执行单元和一种操作浮点单元的方法，使用来自具有多个操作数位置的指令的多个操作数进行乘法/加法运算。浮点单元包括用于计算两个操作数的乘积的乘法器和用于组合所述乘积和三分之一操作数的对准器。第一数据路径用于从指令的第一和第二操作数位置向乘法器操作数提供第二数据路径，并且使用第二数据路径将第三操作数提供给对准器。浮点单元还包括在第二数据路径上的多路复用器，用于为对准器使用来自第二操作数位置的操作数或来自指令的第三操作数位置的操作数。

12. 发明申请

US20050114422A1 High performance implementation of exponent adjustment in a floating point design 失效
标题翻译：浮点设计中指数调整的高性能实现
公开(公告)号：US20050114422A1
公开(公告)日：2005-05-26
申请号：US10718303
申请日：2003-11-20
申请人： Sang Dhong , Silvia Mueller , Hwa-Joon Oh , Kevin Tran
发明人： Sang Dhong , Silvia Mueller , Hwa-Joon Oh , Kevin Tran
IPC分类号： G06F7/00 , G06F7/38 , G06F7/48 , G06F7/483 , G06F7/499 , G06F7/74
CPC分类号： G06F7/483 , G06F7/49947 , G06F7/74
摘要： A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value. Exponent adjust and rounding logic configured to receive the exponent value, the first incremented exponent value, and the second incremented exponent value. The exponent adjust and rounding logic is further configured to add the inverted leading zero signal to the first incremented exponent value and the second incremented exponent value, thereby producing an exponent output value, a first incremented exponent output value, and a second incremented exponent output value. Either the exponent output value, the first incremented exponent output value, or the second exponent output value are then selected.
摘要翻译：一个浮点单元（FPU），产生一个校正信号和一个反向的前导零信号。指数逻辑被配置为生成指数值，第一递增指数值和第二递增指数值。指数调整和舍入逻辑，配置为接收指数值，第一递增指数值和第二递增指数值。指数调整和舍入逻辑还被配置为将反向引导零信号加到第一递增指数值和第二递增指数值，从而产生指数输出值，第一递增指数输出值和第二递增指数输出值。然后选择指数输出值，第一递增指数输出值或第二指数输出值。

13. 发明申请

US20070079193A1 Scannable Latch 有权
标题翻译：可扫描闩锁
公开(公告)号：US20070079193A1
公开(公告)日：2007-04-05
申请号：US11550997
申请日：2006-10-19
申请人： Sang Dhong , Joel Silberman , Osamu Takahashi
发明人： Sang Dhong , Joel Silberman , Osamu Takahashi
IPC分类号： G01R31/28
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译：公开了可扫描的闩锁。可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。

14. 发明申请

US20060270173A1 Methods and apparatus for reducing leakage current in a disabled SOI circuit 有权
标题翻译：用于减少残留SOI电路中漏电流的方法和装置
公开(公告)号：US20060270173A1
公开(公告)日：2006-11-30
申请号：US11137234
申请日：2005-05-25
申请人： Hiroshi Yoshihara , Sang Dhong , Osamu Takahashi , Takaaki Nakazato
发明人： Hiroshi Yoshihara , Sang Dhong , Osamu Takahashi , Takaaki Nakazato
IPC分类号： G06F1/00 , H01L21/8222 , H01L27/12
CPC分类号： H03K19/0016
摘要： Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.
摘要翻译：方法和装置提供了通过使至少一个开关晶体管导通来使能数字电路，使得虚拟接地节点的电压电位基本上等于用于数字电路的电源的接地节点的电压电位，其中数字电路使用绝缘体上硅（SOI）布置中的多个晶体管实现，并且至少一些晶体管参考虚拟接地节点; 以及通过将所述开关晶体管的栅极端子偏压到所述接地节点的电压电位以下来禁止所述数字电路。

15. 发明申请

US20060179176A1 System and method for a memory with combined line and word access 有权
标题翻译：具有组合线和字访问的存储器的系统和方法
公开(公告)号：US20060179176A1
公开(公告)日：2006-08-10
申请号：US11050040
申请日：2005-02-03
申请人： Sang Dhong , Brian Flachs , Harm Hofstee , Osamu Takahashi
发明人： Sang Dhong , Brian Flachs , Harm Hofstee , Osamu Takahashi
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/1626 , G06F13/1663
摘要： A system and method for a processor with memory with combined line and word access are presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank using multiplexers and latches to direct data. The system processes 16 byte load/sore requests using a narrow read/write memory access and also processes 128 byte DMA and instruction fetch requests using a wide read/write memory access. During DMA requests, the system writes/reads sixteen DMA operations to memory on one instruction cycle. By doing this, the memory is available to process load/store or instruction fetch requests during fifteen other instruction cycles.
摘要翻译：提出了一种具有组合线和字访问的存储器的处理器的系统和方法。系统执行窄读/写存储器访问，并使用多路复用器和锁存器对同一存储体进行宽读/写存储器访问以指导数据。该系统使用窄读/写存储器访问处理16字节加载/请求请求，并使用宽读/写存储器访问处理128字节的DMA和指令提取请求。在DMA请求期间，系统在一个指令周期内将16个DMA操作写入/读取存储器。通过这样做，内存可用于在十五个其他指令周期内处理加载/存储或指令提取请求。

16. 发明申请

US20060101364A1 Method and apparatus for data distribution in a high speed processing unit 审中-公开
标题翻译：用于在高速处理单元中进行数据分配的方法和装置
公开(公告)号：US20060101364A1
公开(公告)日：2006-05-11
申请号：US10965625
申请日：2004-10-14
申请人： Sang Dhong , Hiroaki Murakami , Shohji Onishi , Osamu Takahashi
发明人： Sang Dhong , Hiroaki Murakami , Shohji Onishi , Osamu Takahashi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F9/30141
摘要： A method, an apparatus, and a computer program are provided for distributing data in a high speed processing unit. Traditionally, true readout data from multiport register files are inverted multiple times when transmitting the readout to data latches, located at multiple physical layers. The inversion of the readout data can be boost the signals and provide the proper true or complement data to the data latches. To reduce the number of inverters, the register files are configured to output true and complement signals. Therefore, power consumption and area are reduced with the elimination of the inverters.
摘要翻译：提供了一种用于在高速处理单元中分配数据的方法，装置和计算机程序。传统上，当将多个端口寄存器文件的真实读出数据发送到位于多个物理层的数据锁存器时，会反复多次。读出数据的反转可以提升信号，并为数据锁存器提供适当的真实或补充数据。为了减少逆变器的数量，寄存器文件被配置为输出真实和补码信号。因此，随着逆变器的消除，功耗和面积减少。

17. 发明申请

US20060097751A1 Programmable logic array latch 失效
标题翻译：可编程逻辑阵列锁存器
公开(公告)号：US20060097751A1
公开(公告)日：2006-05-11
申请号：US10982018
申请日：2004-11-05
申请人： Sang Dhong , Brian Flachs , Joel Silberman , Osamu Takahashi
发明人： Sang Dhong , Brian Flachs , Joel Silberman , Osamu Takahashi
IPC分类号： H03K19/177
CPC分类号： H03K19/1772
摘要： A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array.
摘要翻译：公开了一种可编程逻辑阵列（PLA）锁存器。 PLA锁存器包括第一逻辑阵列，第二逻辑阵列和仅一个输出锁存器。第二逻辑阵列耦合到第一逻辑阵列。输出锁存器耦合到第二逻辑阵列。

18. 发明申请

US20060095802A1 Scan chain disable function for power saving 失效
标题翻译：扫描链禁用功能进行省电
公开(公告)号：US20060095802A1
公开(公告)日：2006-05-04
申请号：US10976259
申请日：2004-10-28
申请人： Sang Dhong , Joel Silberman , Osamu Takahashi , James Warnock , Dieter Wendel
发明人： Sang Dhong , Joel Silberman , Osamu Takahashi , James Warnock , Dieter Wendel
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/325
摘要： An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.
摘要翻译：提供了一种装置，方法和计算机程序产品，用于通过禁用扫描链来在处理器的功能模式期间节省能量。通过将逻辑门控插入到扫描链中，可以在处理器的功能模式期间禁用扫描链。在功能模式期间，扫描链中锁存位的扫描输出端口切换，这导致不必要的能量消耗。通过门控扫描控制信号和锁存位的扫描输出端口，可以断开锁存位之间的扫描链段。因此，扫描控制信号可以在功能模式下禁用扫描链。

19. 发明授权

US06833736B2 Pulse generating circuit 有权
公开(公告)号：US06833736B2
公开(公告)日：2004-12-21
申请号：US10359805
申请日：2003-02-07
申请人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong , Atsushi Kawasumi
发明人： Takaaki Nakazato , Toru Asano , Osamu Takahashi , Sang Dhong , Atsushi Kawasumi
IPC分类号： H03K908
CPC分类号： H03K5/1565 , H03K5/05 , H03K5/06
摘要： A pulse generator circuit includes a first logic means, a second logic means, a first delay means, and a second delay means. The first logic means is for receiving an input clock signal. The first delay means is for delaying the input clock signal by a first delay time. The second logic means is for receiving a signal output from the first logic means. The second delay means is for delaying the signal output from the first logic means by a second delay time.

20. 发明授权

US08464130B2 Memory device and method thereof 有权
标题翻译：存储器件及其方法
公开(公告)号：US08464130B2
公开(公告)日：2013-06-11
申请号：US12330012
申请日：2008-12-08
申请人： Sang Dhong , Jin Cho , John Wuu , Gurupada Mandal
发明人： Sang Dhong , Jin Cho , John Wuu , Gurupada Mandal
IPC分类号： G06F11/00
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits.
摘要翻译：公开了一种误差校正模块，其中两个比特单元用于以冗余的方式存储一位信息，使得冗余纠错模块可以校正两个比特之一的零星数据错误。

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